[llvm] 236b315 - [RISCV] Remove extra operands from Zcb compression patterns. NFC (#150541)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 24 18:03:32 PDT 2025
Author: Craig Topper
Date: 2025-07-24T18:03:30-07:00
New Revision: 236b315a98900468cc749a618e2204c0d499876a
URL: https://github.com/llvm/llvm-project/commit/236b315a98900468cc749a618e2204c0d499876a
DIFF: https://github.com/llvm/llvm-project/commit/236b315a98900468cc749a618e2204c0d499876a.diff
LOG: [RISCV] Remove extra operands from Zcb compression patterns. NFC (#150541)
Tied operands in the destination are not supposed to be listed. This
didn't cause a functional issue because none of the code noticed that
extra operand was even there.
Simplify verifyDagOpCount to catch this case.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
llvm/utils/TableGen/CompressInstEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
index f1734405fae63..ed1a60aa49cab 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
@@ -291,31 +291,31 @@ def : CompressPat<(MUL GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
let Predicates = [HasStdExtZcb, HasStdExtZbb] in{
def : CompressPat<(SEXT_B GPRC:$rs1, GPRC:$rs1),
- (C_SEXT_B GPRC:$rs1, GPRC:$rs1)>;
+ (C_SEXT_B GPRC:$rs1)>;
def : CompressPat<(SEXT_H GPRC:$rs1, GPRC:$rs1),
- (C_SEXT_H GPRC:$rs1, GPRC:$rs1)>;
+ (C_SEXT_H GPRC:$rs1)>;
} // Predicates = [HasStdExtZcb, HasStdExtZbb]
let Predicates = [HasStdExtZcb, HasStdExtZbb] in{
def : CompressPat<(ZEXT_H_RV32 GPRC:$rs1, GPRC:$rs1),
- (C_ZEXT_H GPRC:$rs1, GPRC:$rs1)>;
+ (C_ZEXT_H GPRC:$rs1)>;
def : CompressPat<(ZEXT_H_RV64 GPRC:$rs1, GPRC:$rs1),
- (C_ZEXT_H GPRC:$rs1, GPRC:$rs1)>;
+ (C_ZEXT_H GPRC:$rs1)>;
} // Predicates = [HasStdExtZcb, HasStdExtZbb]
let Predicates = [HasStdExtZcb] in{
def : CompressPat<(ANDI GPRC:$rs1, GPRC:$rs1, 255),
- (C_ZEXT_B GPRC:$rs1, GPRC:$rs1)>;
+ (C_ZEXT_B GPRC:$rs1)>;
} // Predicates = [HasStdExtZcb]
let Predicates = [HasStdExtZcb, HasStdExtZba, IsRV64] in{
def : CompressPat<(ADD_UW GPRC:$rs1, GPRC:$rs1, X0),
- (C_ZEXT_W GPRC:$rs1, GPRC:$rs1)>;
+ (C_ZEXT_W GPRC:$rs1)>;
} // Predicates = [HasStdExtZcb, HasStdExtZba, IsRV64]
let Predicates = [HasStdExtZcb] in{
def : CompressPat<(XORI GPRC:$rs1, GPRC:$rs1, -1),
- (C_NOT GPRC:$rs1, GPRC:$rs1)>;
+ (C_NOT GPRC:$rs1)>;
}
let Predicates = [HasStdExtZcb] in{
diff --git a/llvm/utils/TableGen/CompressInstEmitter.cpp b/llvm/utils/TableGen/CompressInstEmitter.cpp
index afc892b068582..4665a964bd9e7 100644
--- a/llvm/utils/TableGen/CompressInstEmitter.cpp
+++ b/llvm/utils/TableGen/CompressInstEmitter.cpp
@@ -326,9 +326,6 @@ static bool verifyDagOpCount(const CodeGenInstruction &Inst, const DagInit *Dag,
TiedOpCount++;
}
- if (Dag->getNumArgs() == NumMIOperands)
- return true;
-
// Source instructions are non compressed instructions and have at most one
// tied operand.
if (IsSource && (TiedOpCount > 1))
@@ -336,12 +333,6 @@ static bool verifyDagOpCount(const CodeGenInstruction &Inst, const DagInit *Dag,
"Input operands for Inst '" + Inst.TheDef->getName() +
"' and input Dag operand count mismatch");
- // The Dag can't have more arguments than the Instruction.
- if (Dag->getNumArgs() > NumMIOperands)
- PrintFatalError(Inst.TheDef->getLoc(),
- "Inst '" + Inst.TheDef->getName() +
- "' and Dag operand count mismatch");
-
// The Instruction might have tied operands so the Dag might have
// a fewer operand count.
if (Dag->getNumArgs() != (NumMIOperands - TiedOpCount))
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