[llvm] [AMDGPU] narrow only on store to pow of 2 mem location (PR #150093)

[Tiger Ding via llvm-commits]

zerogtiger wrote:

Seems like weird sizes like i65 is used, though is quite rare. I've found an example of lowering to i65 in some polly passes with opt: https://github.com/llvm/llvm-project/blob/main/polly/test/CodeGen/partial_write_in_region_with_loop.ll

https://github.com/llvm/llvm-project/pull/150093