[llvm] [DAG] visitFREEZE - enable SRA/SRL handling (PR #148252)

[Craig Topper via llvm-commits]

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@@ -231,17 +232,19 @@ define i32 @ctlz_lshr_i32(i32 signext %a) {
 ; RV64I-NEXT:    srliw a0, a0, 1
 ; RV64I-NEXT:    beqz a0, .LBB4_2
 ; RV64I-NEXT:  # %bb.1: # %cond.false
-; RV64I-NEXT:    srliw a1, a0, 1
+; RV64I-NEXT:    srli a1, a0, 1
 ; RV64I-NEXT:    lui a2, 349525
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    addi a1, a2, 1365
-; RV64I-NEXT:    srliw a2, a0, 2
+; RV64I-NEXT:    srli a2, a0, 2
 ; RV64I-NEXT:    or a0, a0, a2
-; RV64I-NEXT:    srliw a2, a0, 4
+; RV64I-NEXT:    srli a2, a0, 4
 ; RV64I-NEXT:    or a0, a0, a2
-; RV64I-NEXT:    srliw a2, a0, 8
+; RV64I-NEXT:    slli a2, a0, 33
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topperc wrote:

I think the issue here is that we moved a freeze in the entry block which allowed computeKnownBits to compute a value for the output of the block. Then an AssertZExt was emitted in the the cond.false block. This allowed us to remove some bits from the AND mask and our isel code for srliw doesn't use computeKnownBits to fill in missing bits.

https://github.com/llvm/llvm-project/pull/148252