[llvm] [AMDGPU] Constrain AV->VReg if we do not exceed RP thresholds (PR #150086)

[Lucas Ramirez via llvm-commits]

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@@ -250,9 +252,15 @@ class GCNScheduleDAGMILive final : public ScheduleDAGMILive {
   // limit. Register pressure in these regions usually will result in spilling.
   BitVector RegionsWithExcessRP;
 
+  // Regions that have VGPR RP which exceed the addressable limit.
+  BitVector RegionsWithExcessVGPRRP;
+
   // Regions that has the same occupancy as the latest MinOccupancy
   BitVector RegionsWithMinOcc;
 
+  // Regions which use the AV RC.
+  BitVector RegionsWithAVRegs;
+
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lucas-rami wrote:

Can these two bitvectors be internal to the new stage instead? This avoids recomputation between all other stages that don't care about them and eliminates the possibility that we forget to keep them up to date (after a scheduling revert for example).

https://github.com/llvm/llvm-project/pull/150086