[llvm] fd86b2e - [RISCV][llvm-exegesis] Add missing operand frm for FCVT_D_W (#149989)

[via llvm-commits]

Author: Jim Lin
Date: 2025-07-24T08:53:09+08:00
New Revision: fd86b2e26c0933c2af61fc50a674f668a7991f66

URL: https://github.com/llvm/llvm-project/commit/fd86b2e26c0933c2af61fc50a674f668a7991f66
DIFF: https://github.com/llvm/llvm-project/commit/fd86b2e26c0933c2af61fc50a674f668a7991f66.diff

LOG: [RISCV][llvm-exegesis] Add missing operand frm for FCVT_D_W (#149989)

We encountered the index of operand out of bounds crash because FCVT_D_W
lacks frm operand.

Added: 
    llvm/test/tools/llvm-exegesis/RISCV/set-reg-init-check.s

Modified: 
    llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/test/tools/llvm-exegesis/RISCV/set-reg-init-check.s b/llvm/test/tools/llvm-exegesis/RISCV/set-reg-init-check.s
new file mode 100644
index 0000000000000..153e86aed9552
--- /dev/null
+++ b/llvm/test/tools/llvm-exegesis/RISCV/set-reg-init-check.s
@@ -0,0 +1,7 @@
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv32-unknown-linux-gnu --mcpu=generic --dump-object-to-disk=%d --benchmark-phase=assemble-measured-code --opcode-name=FADD_D -mattr="+d" 2>&1
+# RUN: llvm-objdump -M numeric -d %d > %t.s
+# RUN: FileCheck %s < %t.s
+
+CHECK:       <foo>:
+CHECK:       li       x30, 0x0
+CHECK-NEXT:  fcvt.d.w f{{[0-9]|[12][0-9]|3[01]}}, x30

diff  --git a/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp b/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
index 676479b3d5792..ea830bd5f753d 100644
--- a/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
@@ -651,8 +651,10 @@ static std::vector<MCInst> loadFP64RegBits32(const MCSubtargetInfo &STI,
   }
 
   std::vector<MCInst> Instrs = loadIntReg(STI, ScratchIntReg, Bits);
-  Instrs.push_back(
-      MCInstBuilder(RISCV::FCVT_D_W).addReg(Reg).addReg(ScratchIntReg));
+  Instrs.push_back(MCInstBuilder(RISCV::FCVT_D_W)
+                       .addReg(Reg)
+                       .addReg(ScratchIntReg)
+                       .addImm(RISCVFPRndMode::RNE));
   return Instrs;
 }