[llvm] [AMDGPU] Constrain AV->VReg if we do not exceed RP thresholds (PR #150086)

[Matt Arsenault via llvm-commits]

================
@@ -1036,6 +1046,78 @@ bool GCNSchedStage::initGCNSchedStage() {
   return true;
 }
 
+bool AVGPRRewriteScheduleStage::reconstrainRegClass(
+    Register Reg, const TargetRegisterClass *NewRC) const {
+  const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
----------------
arsenm wrote:

```suggestion
  const SIInstrInfo *TII = MF.getSubtarget<GCNSubtarget>().getInstrInfo();
```

https://github.com/llvm/llvm-project/pull/150086