[llvm] [SelectionDAG] Verify SDTCisVT and SDTCVecEltisVT constraints (PR #150125)

[Sergei Barannikov via llvm-commits]

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@@ -125,4 +148,86 @@ void SDNodeInfo::verifyNode(const SelectionDAG &DAG, const SDNode *N) const {
                             " must be Register or RegisterMask");
     }
   }
+
+  unsigned VTHwMode =
+      DAG.getSubtarget().getHwMode(MCSubtargetInfo::HwMode_ValueType);
+
+  auto GetConstraintOp = [&](unsigned Idx) {
+    if (Idx < Desc.NumResults)
+      return ConstraintOp{N, Idx, /*IsRes=*/true};
+    return ConstraintOp{N, HasChain + (Idx - Desc.NumResults), /*IsRes=*/false};
+  };
+
+  auto GetConstraintVT = [&](const SDTypeConstraint &C) {
+    if (!C.NumHwModes)
+      return static_cast<MVT::SimpleValueType>(C.VT);
+    for (auto [Mode, VT] : ArrayRef(&VTByHwModeTable[C.VT], C.NumHwModes))
+      if (Mode == VTHwMode)
+        return VT;
+    llvm_unreachable("No value type for this HW mode");
+  };
+
+  SmallString<128> ES;
+  raw_svector_ostream SS(ES);
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s-barannikov wrote:

Thanks, will do that after implementing more constraint checks.


https://github.com/llvm/llvm-project/pull/150125