[llvm] [RISCV][llvm-exegesis] Add missing operand frm for FCVT_D_W (PR #149989)

[Jim Lin via llvm-commits]

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/149989

>From 33b313b64ed23de49e2857306fcdc47ec044cfdf Mon Sep 17 00:00:00 2001
From: Jim Lin <jim at andestech.com>
Date: Tue, 22 Jul 2025 15:59:44 +0800
Subject: [PATCH 1/5] [RISCV][llvm-exegesis] Add missing operand frm for
 FCVT_D_W

We encountered the index of operand out of bounds crash because FCVT_D_W lacks frm operand.
---
 llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp b/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
index 676479b3d5792..d54df2b5dc0ef 100644
--- a/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
@@ -651,8 +651,10 @@ static std::vector<MCInst> loadFP64RegBits32(const MCSubtargetInfo &STI,
   }
 
   std::vector<MCInst> Instrs = loadIntReg(STI, ScratchIntReg, Bits);
-  Instrs.push_back(
-      MCInstBuilder(RISCV::FCVT_D_W).addReg(Reg).addReg(ScratchIntReg));
+  Instrs.push_back(MCInstBuilder(RISCV::FCVT_D_W)
+                       .addReg(Reg)
+                       .addReg(ScratchIntReg)
+                       .addImm(7));
   return Instrs;
 }
 

>From 3d5d1e5b98dc36f2350ee0eb4041d743b3df508e Mon Sep 17 00:00:00 2001
From: Jim Lin <jim at andestech.com>
Date: Wed, 23 Jul 2025 10:44:01 +0800
Subject: [PATCH 2/5] Add testcase

---
 llvm/test/tools/llvm-exegesis/RISCV/set-reg-init-check.s | 7 +++++++
 1 file changed, 7 insertions(+)
 create mode 100644 llvm/test/tools/llvm-exegesis/RISCV/set-reg-init-check.s

diff --git a/llvm/test/tools/llvm-exegesis/RISCV/set-reg-init-check.s b/llvm/test/tools/llvm-exegesis/RISCV/set-reg-init-check.s
new file mode 100644
index 0000000000000..f75c80ef4191b
--- /dev/null
+++ b/llvm/test/tools/llvm-exegesis/RISCV/set-reg-init-check.s
@@ -0,0 +1,7 @@
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv32-unknown-linux-gnu --mcpu=generic --dump-object-to-disk=%d --benchmark-phase=assemble-measured-code --opcode-name=FADD_D -mattr="+d" 2>&1
+# RUN: llvm-objdump -M numeric -d %d > %t.s
+# RUN: FileCheck %s --check-prefix=FCVT_D_W_ASM < %t.s
+
+FCVT_D_W_ASM:       <foo>:
+FCVT_D_W_ASM:       li       x30, 0x0
+FCVT_D_W_ASM-NEXT:  fcvt.d.w f{{[0-9]|[12][0-9]|3[01]}}, x30

>From 2071318e0adf1eda4b07716f76fbb50b111c5936 Mon Sep 17 00:00:00 2001
From: Jim Lin <jim at andestech.com>
Date: Wed, 23 Jul 2025 10:46:10 +0800
Subject: [PATCH 3/5] Use the enum from RISCVBaseInfo.h and change it to RNE
 (imm = 0)

---
 llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp b/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
index d54df2b5dc0ef..77e0e435e1b8c 100644
--- a/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
@@ -654,7 +654,7 @@ static std::vector<MCInst> loadFP64RegBits32(const MCSubtargetInfo &STI,
   Instrs.push_back(MCInstBuilder(RISCV::FCVT_D_W)
                        .addReg(Reg)
                        .addReg(ScratchIntReg)
-                       .addImm(7));
+                       .addImm(RISCVFPRndMode::RoundingMode::RNE));
   return Instrs;
 }
 

>From 4025094a98620295db97b32dd1136f96742aaa92 Mon Sep 17 00:00:00 2001
From: Jim Lin <jim at andestech.com>
Date: Wed, 23 Jul 2025 13:07:27 +0800
Subject: [PATCH 4/5] Use RISCVFPRndMode::RNE instead

---
 llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp b/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
index 77e0e435e1b8c..ea830bd5f753d 100644
--- a/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
@@ -654,7 +654,7 @@ static std::vector<MCInst> loadFP64RegBits32(const MCSubtargetInfo &STI,
   Instrs.push_back(MCInstBuilder(RISCV::FCVT_D_W)
                        .addReg(Reg)
                        .addReg(ScratchIntReg)
-                       .addImm(RISCVFPRndMode::RoundingMode::RNE));
+                       .addImm(RISCVFPRndMode::RNE));
   return Instrs;
 }
 

>From 77ae587fccb2016e714f693558989ae7f237755d Mon Sep 17 00:00:00 2001
From: Jim Lin <jim at andestech.com>
Date: Wed, 23 Jul 2025 13:08:41 +0800
Subject: [PATCH 5/5] Use default `CHECK` prefix

---
 llvm/test/tools/llvm-exegesis/RISCV/set-reg-init-check.s | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/llvm/test/tools/llvm-exegesis/RISCV/set-reg-init-check.s b/llvm/test/tools/llvm-exegesis/RISCV/set-reg-init-check.s
index f75c80ef4191b..153e86aed9552 100644
--- a/llvm/test/tools/llvm-exegesis/RISCV/set-reg-init-check.s
+++ b/llvm/test/tools/llvm-exegesis/RISCV/set-reg-init-check.s
@@ -1,7 +1,7 @@
 # RUN: llvm-exegesis -mode=latency -mtriple=riscv32-unknown-linux-gnu --mcpu=generic --dump-object-to-disk=%d --benchmark-phase=assemble-measured-code --opcode-name=FADD_D -mattr="+d" 2>&1
 # RUN: llvm-objdump -M numeric -d %d > %t.s
-# RUN: FileCheck %s --check-prefix=FCVT_D_W_ASM < %t.s
+# RUN: FileCheck %s < %t.s
 
-FCVT_D_W_ASM:       <foo>:
-FCVT_D_W_ASM:       li       x30, 0x0
-FCVT_D_W_ASM-NEXT:  fcvt.d.w f{{[0-9]|[12][0-9]|3[01]}}, x30
+CHECK:       <foo>:
+CHECK:       li       x30, 0x0
+CHECK-NEXT:  fcvt.d.w f{{[0-9]|[12][0-9]|3[01]}}, x30