[llvm] [PowerPC] Exploit xxeval instruction for ternary patterns - part 1 (PR #141733)

[Tony Varghese via llvm-commits]

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@@ -2159,8 +2159,118 @@ let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX] in {
                                (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
 }
 
-class XXEvalPattern <dag pattern, bits<8> imm> :
-  Pat<(v4i32 pattern), (XXEVAL $vA, $vB, $vC, imm)> {}
+  // =============================================================================
+  // XXEVAL Instruction Pattern Definitions
+  // =============================================================================
+  // 
+  // XXEVAL instruction performs 256 different logical operations on three vector 
+  // operands using an 8-bit immediate value to select the operation.
+  // Format: xxeval XT, XA, XB, XC, IMM 
+  // For example:
+  // Equivalent function A?xor(B,C):and(B,C) is performed if the IMM value is 22.
+  //
+  // REGISTER CLASS CONSTRAINTS:
+  // - XXEVAL natively supports: VSRC register class [v4i32, v4f32, v2f64, v2i64]  
+  // - Other vector types [v16i8, v8i16] require COPY_TO_REGCLASS to/from VRRC
+  // =============================================================================
+
+  // Auto-detect if type needs VRRC register class conversion. This is useful for 
+  // xxeval pattern matching.
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tonykuttai wrote:

git clang-format does not work on tablegen files. I did manually fix the formatting.

https://github.com/llvm/llvm-project/pull/141733