[llvm] [DAG] optimize llvm.ucmp for 1-bit inputs to return subtraction of operands (PR #150058)

[Craig Topper via llvm-commits]

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@@ -10942,6 +10942,10 @@ SDValue TargetLowering::expandCMP(SDNode *Node, SelectionDAG &DAG) const {
   SDValue IsLT = DAG.getSetCC(dl, BoolVT, LHS, RHS, LTPredicate);
   SDValue IsGT = DAG.getSetCC(dl, BoolVT, LHS, RHS, GTPredicate);
 
+  if (isa<VTSDNode>(RHS->getOperand(1)) &&
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topperc wrote:

You can't access operand 1 without confirming the opcode of RHS first to know that operand 1 exists.

The only opcode that has a VTSDNode operand is SIGN_EXTEND_INREG, but your test uses `zeroext` so I don't know where a SIGN_EXTEND_INREG would come from.

https://github.com/llvm/llvm-project/pull/150058