[llvm] [AArch64][CodeGen] Optimize register zero initialization in svsub_x (PR #149840)

[Sjoerd Meijer via llvm-commits]

sjoerdmeijer wrote:

> They both do the same thing and clear the entire register. You can see the "Zero Latency MOVs" section of the SWOG for the instructions that are more efficiently executed, AFAUI they are both on there so should perform the same.

I agree with this. And if generating the same code as GCC is a weak argument, maybe we should drop this?

https://github.com/llvm/llvm-project/pull/149840