[llvm] [RISCV] Rewrite deinterleave load as vlse optimization as DAG combine (PR #150049)

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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp -- llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
``````````

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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 1e0503071..1a7b0fa3f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -20773,14 +20773,29 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
 
     unsigned NF = 0;
     switch (Tuple.getConstantOperandVal(1)) {
-    default: break;
-    case Intrinsic::riscv_vlseg2_mask: NF = 2; break;
-    case Intrinsic::riscv_vlseg3_mask: NF = 3; break;
-    case Intrinsic::riscv_vlseg4_mask: NF = 4; break;
-    case Intrinsic::riscv_vlseg5_mask: NF = 5; break;
-    case Intrinsic::riscv_vlseg6_mask: NF = 6; break;
-    case Intrinsic::riscv_vlseg7_mask: NF = 7; break;
-    case Intrinsic::riscv_vlseg8_mask: NF = 8; break;
+    default:
+      break;
+    case Intrinsic::riscv_vlseg2_mask:
+      NF = 2;
+      break;
+    case Intrinsic::riscv_vlseg3_mask:
+      NF = 3;
+      break;
+    case Intrinsic::riscv_vlseg4_mask:
+      NF = 4;
+      break;
+    case Intrinsic::riscv_vlseg5_mask:
+      NF = 5;
+      break;
+    case Intrinsic::riscv_vlseg6_mask:
+      NF = 6;
+      break;
+    case Intrinsic::riscv_vlseg7_mask:
+      NF = 7;
+      break;
+    case Intrinsic::riscv_vlseg8_mask:
+      NF = 8;
+      break;
     }
     if (!NF || Subtarget.hasOptimizedSegmentLoadStore(NF))
       break;
@@ -20789,26 +20804,25 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
     unsigned SEW = VT.getScalarSizeInBits();
     if (Log2_64(SEW) != Tuple.getConstantOperandVal(7))
       break;
-    unsigned Stride = SEW/8 * NF;
-    SDValue Offset = DAG.getConstant(SEW/8 * Idx, DL, XLenVT);
+    unsigned Stride = SEW / 8 * NF;
+    SDValue Offset = DAG.getConstant(SEW / 8 * Idx, DL, XLenVT);
 
     SDValue Ops[] = {
-      /*Chain=*/Tuple.getOperand(0),
-      /*IntID=*/DAG.getTargetConstant(Intrinsic::riscv_vlse_mask, DL, XLenVT),
-      /*Passthru=*/Tuple.getOperand(2),
-      /*Ptr=*/DAG.getNode(ISD::ADD, DL, XLenVT, Tuple.getOperand(3), Offset),
-      /*Stride=*/DAG.getConstant(Stride, DL, XLenVT),
-      /*Mask=*/Tuple.getOperand(4),
-      /*VL=*/Tuple.getOperand(5),
-      /*Policy=*/Tuple.getOperand(6)
-    };
+        /*Chain=*/Tuple.getOperand(0),
+        /*IntID=*/DAG.getTargetConstant(Intrinsic::riscv_vlse_mask, DL, XLenVT),
+        /*Passthru=*/Tuple.getOperand(2),
+        /*Ptr=*/DAG.getNode(ISD::ADD, DL, XLenVT, Tuple.getOperand(3), Offset),
+        /*Stride=*/DAG.getConstant(Stride, DL, XLenVT),
+        /*Mask=*/Tuple.getOperand(4),
+        /*VL=*/Tuple.getOperand(5),
+        /*Policy=*/Tuple.getOperand(6)};
 
     SDVTList VTs = DAG.getVTList({VT, MVT::Other});
     // @REVIEWERS - What's the right MemVT and MMO to use here?
-    SDValue Result =
-      DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, VTs, Ops,
-                              cast<MemIntrinsicSDNode>(Tuple)->getMemoryVT(),
-                              cast<MemIntrinsicSDNode>(Tuple)->getMemOperand());
+    SDValue Result = DAG.getMemIntrinsicNode(
+        ISD::INTRINSIC_W_CHAIN, DL, VTs, Ops,
+        cast<MemIntrinsicSDNode>(Tuple)->getMemoryVT(),
+        cast<MemIntrinsicSDNode>(Tuple)->getMemOperand());
     SDValue Chain = Result.getValue(1);
     return DAG.getMergeValues({Result, Chain}, DL);
   }

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https://github.com/llvm/llvm-project/pull/150049