[llvm] [NFC][AMDGPU] Remove `-verify-machineinstrs` from `llvm/test/CodeGen/MIR/AMDGPU/` (PR #150046)
Shilei Tian via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 22 08:46:12 PDT 2025
https://github.com/shiltian created https://github.com/llvm/llvm-project/pull/150046
Similar to #150024, this one is for `llvm/test/CodeGen/MIR/AMDGPU/`.
>From 0923b60eaf2e52791fb0c8ecd8ee47d4c4b67249 Mon Sep 17 00:00:00 2001
From: Shilei Tian <i at tianshilei.me>
Date: Tue, 22 Jul 2025 11:42:12 -0400
Subject: [PATCH] [NFC][AMDGPU] Remove `-verify-machineinstrs` from
`llvm/test/CodeGen/MIR/AMDGPU/`
Similar to #150024, this one is for `llvm/test/CodeGen/MIR/AMDGPU/`.
---
llvm/test/CodeGen/MIR/AMDGPU/custom-pseudo-source-values.ll | 2 +-
.../MIR/AMDGPU/invalid-frame-index-invalid-fixed-stack.mir | 2 +-
.../MIR/AMDGPU/invalid-frame-index-invalid-stack.mir | 2 +-
.../CodeGen/MIR/AMDGPU/invalid-frame-index-no-stack.mir | 2 +-
llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index.mir | 2 +-
llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index2.mir | 2 +-
.../CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll | 2 +-
.../CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll | 2 +-
.../machine-function-info-dynlds-align-invalid-case.mir | 2 +-
.../AMDGPU/machine-function-info-long-branch-reg-debug.ll | 2 +-
.../MIR/AMDGPU/machine-function-info-long-branch-reg.ll | 2 +-
.../test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir | 4 ++--
llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll | 2 +-
llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir | 4 ++--
llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir | 4 ++--
llvm/test/CodeGen/MIR/AMDGPU/noconvergent-invalid.mir | 2 +-
llvm/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir | 6 +++---
llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir | 2 +-
llvm/test/CodeGen/MIR/AMDGPU/subreg-def-is-not-ssa.mir | 2 +-
.../CodeGen/MIR/AMDGPU/vgpr-for-agpr-copy-invalid-reg.mir | 2 +-
.../CodeGen/MIR/AMDGPU/wwm-reserved-regs-invalid-reg.mir | 2 +-
.../test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-not-a-reg.mir | 2 +-
llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs.mir | 4 ++--
23 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/custom-pseudo-source-values.ll b/llvm/test/CodeGen/MIR/AMDGPU/custom-pseudo-source-values.ll
index ed57628fa721c..91ce5573d1052 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/custom-pseudo-source-values.ll
+++ b/llvm/test/CodeGen/MIR/AMDGPU/custom-pseudo-source-values.ll
@@ -1,5 +1,5 @@
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after finalize-isel -o %t.mir %s
-; RUN: llc -run-pass=none -verify-machineinstrs %t.mir -o - | FileCheck %s
+; RUN: llc -run-pass=none %t.mir -o - | FileCheck %s
; Test that custom pseudo source values can be round trip serialized through MIR.
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-fixed-stack.mir b/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-fixed-stack.mir
index 097f0f8c886ac..f1b9fe4c01a85 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-fixed-stack.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-fixed-stack.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o /dev/null 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none %s -o /dev/null 2>&1 | FileCheck %s
---
name: invalid_scavenge_fi
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-stack.mir b/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-stack.mir
index 278db8c3c375e..efc7f6569148a 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-stack.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-stack.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o /dev/null 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none %s -o /dev/null 2>&1 | FileCheck %s
---
name: invalid_scavenge_fi
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-no-stack.mir b/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-no-stack.mir
index 0ec4e2802a29d..26392c0ed59f6 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-no-stack.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-no-stack.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o /dev/null 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none %s -o /dev/null 2>&1 | FileCheck %s
---
name: invalid_scavenge_fi
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index.mir b/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index.mir
index f539a12db35b3..16af286106212 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o /dev/null 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none %s -o /dev/null 2>&1 | FileCheck %s
---
name: invalid_scavenge_fi
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index2.mir b/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index2.mir
index 203fdfbb75ab3..c9ddbdcbb28f1 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index2.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index2.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o /dev/null 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none %s -o /dev/null 2>&1 | FileCheck %s
---
name: invalid_scavenge_fi
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll b/llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll
index 278cf0150c2f7..ee998d8ab622b 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll
+++ b/llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn -verify-machineinstrs -amdgpu-s-branch-bits=5 -stop-after=branch-relaxation %s -o - | FileCheck %s
+; RUN: llc -mtriple=amdgcn -amdgpu-s-branch-bits=5 -stop-after=branch-relaxation %s -o - | FileCheck %s
; Test long branch reserved register pass when all
; SGPRs are used
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
index 890ea44081ce7..62afab938de23 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -amdgpu-spill-sgpr-to-vgpr=0 -stop-after prologepilog -verify-machineinstrs %s -o - | FileCheck -check-prefix=AFTER-PEI %s
+; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -amdgpu-spill-sgpr-to-vgpr=0 -stop-after prologepilog %s -o - | FileCheck -check-prefix=AFTER-PEI %s
; Test that the ScavengeFI is serialized in the SIMachineFunctionInfo.
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-dynlds-align-invalid-case.mir b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-dynlds-align-invalid-case.mir
index be12301b1431a..4b7e08a8e35a9 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-dynlds-align-invalid-case.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-dynlds-align-invalid-case.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none %s -o - 2>&1 | FileCheck %s
---
# CHECK: error: YAML:8:16: must be a power of two
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll
index f84ef8a3844dd..7d9b48b769d2d 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -amdgpu-s-branch-bits=4 -stop-after=branch-relaxation -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-s-branch-bits=4 -stop-after=branch-relaxation %s -o - | FileCheck %s
; Test that debug instructions do not change long branch reserved serialized through
; MIR.
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll
index cc834d017c149..81d71b2f58ead 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -amdgpu-s-branch-bits=4 -stop-after=branch-relaxation -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-s-branch-bits=4 -stop-after=branch-relaxation %s -o - | FileCheck %s
; Test that long branch reserved register is serialized through
; MIR.
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
index 06c580ec6f6b4..b67d2b4fff248 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o - | FileCheck -check-prefixes=FULL,ALL %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefixes=SIMPLE,ALL %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=none %s -o - | FileCheck -check-prefixes=FULL,ALL %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -simplify-mir %s -o - | FileCheck -check-prefixes=SIMPLE,ALL %s
---
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
index 427154651a381..acdb1f8fa0d32 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
@@ -1,5 +1,5 @@
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after=si-pre-allocate-wwm-regs -o %t.mir %s
-; RUN: llc -run-pass=none -verify-machineinstrs %t.mir -o - | FileCheck %s
+; RUN: llc -run-pass=none %t.mir -o - | FileCheck %s
; Test that SIMachineFunctionInfo can be round trip serialized through
; MIR.
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir b/llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
index c67f7e662ef02..cc5ba1e03479f 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
@@ -1,5 +1,5 @@
-# RUN: llc -o - -mtriple=amdgcn -run-pass mir-canonicalizer -verify-machineinstrs %s | FileCheck %s
-# RUN: llc -o - -mtriple=amdgcn -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -o - -mtriple=amdgcn -run-pass mir-canonicalizer %s | FileCheck %s
+# RUN: llc -o - -mtriple=amdgcn -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash %s | FileCheck %s
# This tests for the itereator invalidation fix (reviews.llvm.org/D62713)
...
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir b/llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir
index aa30e20dd7f06..1d0d2e3e9db21 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass mir-canonicalizer -verify-machineinstrs -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass mir-canonicalizer -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -o - %s | FileCheck %s
--- |
target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/noconvergent-invalid.mir b/llvm/test/CodeGen/MIR/AMDGPU/noconvergent-invalid.mir
index b674629cc5f02..a3a30baa72e99 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/noconvergent-invalid.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/noconvergent-invalid.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o /dev/null 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -run-pass=none %s -o /dev/null 2>&1 | FileCheck %s
---
name: noconvergent_invalid
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir b/llvm/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
index ff66323826ac1..f7bb45464db64 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
@@ -1,6 +1,6 @@
-# RUN: llc -mtriple=amdgcn -run-pass=none -verify-machineinstrs -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn -run-pass mir-canonicalizer -verify-machineinstrs -o - %s
-# RUN: llc -mtriple=amdgcn -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs -o - %s
+# RUN: llc -mtriple=amdgcn -run-pass=none -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -run-pass mir-canonicalizer -o - %s
+# RUN: llc -mtriple=amdgcn -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -o - %s
# Previously getReservedRegs was called before parsing
# machineFunctionInfo, but the AMDGPU implementation depends on
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir b/llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir
index 9831f786b847d..9955f717b97a3 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir
@@ -3,7 +3,7 @@
# contains not dead objects only. So using objects IDs as offset in the storage
# caused out of bounds access.
-# RUN: llc -mtriple=amdgcn -start-before=si-lower-sgpr-spills -stop-after=prologepilog -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -start-before=si-lower-sgpr-spills -stop-after=prologepilog -o - %s | FileCheck %s
# CHECK-LABEL: name: foo
# CHECK: {{^}}fixedStack: []
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/subreg-def-is-not-ssa.mir b/llvm/test/CodeGen/MIR/AMDGPU/subreg-def-is-not-ssa.mir
index 9020deb854708..1dbbf90d49ea9 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/subreg-def-is-not-ssa.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/subreg-def-is-not-ssa.mir
@@ -1,5 +1,5 @@
# REQUIRES: asserts
-# RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -o /dev/null %s 2>&1 | FileCheck %s
# CHECK: MachineFunctionProperties required by InstructionSelect pass are not met by function subreg_def_is_not_ssa.
# CHECK-NEXT: Required properties: IsSSA
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/vgpr-for-agpr-copy-invalid-reg.mir b/llvm/test/CodeGen/MIR/AMDGPU/vgpr-for-agpr-copy-invalid-reg.mir
index 80f07e07569a3..82801f1449fe5 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/vgpr-for-agpr-copy-invalid-reg.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/vgpr-for-agpr-copy-invalid-reg.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o /dev/null 2>&1 | FileCheck -check-prefix=ERR %s
+# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none %s -o /dev/null 2>&1 | FileCheck -check-prefix=ERR %s
---
name: invalid_reg
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-invalid-reg.mir b/llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-invalid-reg.mir
index cd1ac22e85bea..735df8b1d20b8 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-invalid-reg.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-invalid-reg.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o /dev/null 2>&1 | FileCheck -check-prefix=ERR %s
+# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none %s -o /dev/null 2>&1 | FileCheck -check-prefix=ERR %s
---
name: invalid_reg
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-not-a-reg.mir b/llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-not-a-reg.mir
index d1c08791d1fa5..3e5e0b94bc93b 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-not-a-reg.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-not-a-reg.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o /dev/null 2>&1 | FileCheck -check-prefix=ERR %s
+# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none %s -o /dev/null 2>&1 | FileCheck -check-prefix=ERR %s
---
name: invalid_reg
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs.mir b/llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs.mir
index 128e73f2f44e9..4f92ceaa87ef7 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o - | FileCheck %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=none %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -simplify-mir %s -o - | FileCheck %s
# CHECK-LABEL: name: empty_wwm_regs{{$}}
# CHECK: machineFunctionInfo:
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