[llvm] [RISCV][llvm-exegesis] Add missing operand frm for FCVT_D_W (PR #149989)

[Aiden Grossman via llvm-commits]

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@@ -651,8 +651,10 @@ static std::vector<MCInst> loadFP64RegBits32(const MCSubtargetInfo &STI,
   }
 
   std::vector<MCInst> Instrs = loadIntReg(STI, ScratchIntReg, Bits);
-  Instrs.push_back(
-      MCInstBuilder(RISCV::FCVT_D_W).addReg(Reg).addReg(ScratchIntReg));
+  Instrs.push_back(MCInstBuilder(RISCV::FCVT_D_W)
+                       .addReg(Reg)
+                       .addReg(ScratchIntReg)
+                       .addImm(7));
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boomanaiden154 wrote:

I believe it's the rounding mode if I'm understanding the ISA docs correctly. It would also be good to have in the comment what rounding mode `0x7` corresponds to and why we're using that one.

https://github.com/llvm/llvm-project/pull/149989