[llvm] [AArch64] Removed redundant FMOV instruction for truncstores of f64 via bitcast to i64. (PR #149997)

[Amina Chabane via llvm-commits]

https://github.com/Amichaxx created https://github.com/llvm/llvm-project/pull/149997

Previously, storing the low bits of a double, which was bitcast to i64 and truncated to i32 or i16, would emit a redundant FMOV. This patch introduces new TableGen patterns to avoid the unnecessary FMOV. Tests added: bitcast_truncstore.ll

>From ac85477cb000cea273922c73f08b729bdd9e6dee Mon Sep 17 00:00:00 2001
From: Amina Chabane <amina.chabane at arm.com>
Date: Tue, 22 Jul 2025 10:56:27 +0000
Subject: [PATCH] [AArch64] Removed redundant FMOV instruction for truncstores
 of f64 via bitcast to i64. Previously, storing the low bits of a double,
 which was bitcast to i64 and truncated to i32 or i16, would emit a redundant
 FMOV. This patch introduces new TableGen patterns to avoid the unnecessary
 FMOV. Tests added: bitcast_truncstore.ll

---
 llvm/lib/Target/AArch64/AArch64InstrInfo.td   |  8 ++++++
 .../CodeGen/AArch64/bitcast_truncstore.ll     | 26 +++++++++++++++++++
 2 files changed, 34 insertions(+)
 create mode 100644 llvm/test/CodeGen/AArch64/bitcast_truncstore.ll

diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 0cb7b02d84a6e..aa635b188da70 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -4649,6 +4649,14 @@ let Predicates = [IsLE] in {
             (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
 }
 
+// truncstorei32 of f64 bitcasted to i64
+def : Pat<(truncstorei32 (i64 (bitconvert (f64 FPR64:$Rt))), (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),
+          (STRSui (EXTRACT_SUBREG FPR64:$Rt, ssub), GPR64sp:$Rn, uimm12s4:$offset)>;
+
+// truncstorei16 of f64 bitcasted to i64
+def : Pat<(truncstorei16 (i64 (bitconvert (f64 FPR64:$Rt))), (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
+          (STRHui (f16 (EXTRACT_SUBREG FPR64:$Rt, hsub)), GPR64sp:$Rn, uimm12s2:$offset)>;     
+
 // truncstore i64
 def : Pat<(truncstorei32 GPR64:$Rt,
                          (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),
diff --git a/llvm/test/CodeGen/AArch64/bitcast_truncstore.ll b/llvm/test/CodeGen/AArch64/bitcast_truncstore.ll
new file mode 100644
index 0000000000000..8e0d0c2158090
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/bitcast_truncstore.ll
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s
+
+define void @_Z10store_i64_from_f64Pjd(ptr %n, double noundef %x){
+; CHECK-LABEL: _Z10store_i64_from_f64Pjd:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    str s0, [x0]
+; CHECK-NEXT:    ret
+entry:
+  %0 = bitcast double %x to i64
+  %conv = trunc i64 %0 to i32
+  store i32 %conv, ptr %n, align 4
+  ret void
+}
+
+define void @_Z9store_i16Ptd(ptr %n, double noundef %x) {
+; CHECK-LABEL: _Z9store_i16Ptd:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    str h0, [x0]
+; CHECK-NEXT:    ret
+entry:
+  %0 = bitcast double %x to i64
+  %conv = trunc i64 %0 to i16
+  store i16 %conv, ptr %n, align 2
+  ret void
+}