[llvm] [RISCV][llvm-exegesis] Add missing operand frm for FCVT_D_W (PR #149989)

via llvm-commits llvm-commits at lists.llvm.org
Tue Jul 22 02:55:29 PDT 2025


llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Jim Lin (tclin914)

<details>
<summary>Changes</summary>

We encountered the index of operand out of bounds crash because FCVT_D_W lacks frm operand.

---
Full diff: https://github.com/llvm/llvm-project/pull/149989.diff


1 Files Affected:

- (modified) llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp (+4-2) 


``````````diff
diff --git a/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp b/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
index 676479b3d5792..d54df2b5dc0ef 100644
--- a/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
@@ -651,8 +651,10 @@ static std::vector<MCInst> loadFP64RegBits32(const MCSubtargetInfo &STI,
   }
 
   std::vector<MCInst> Instrs = loadIntReg(STI, ScratchIntReg, Bits);
-  Instrs.push_back(
-      MCInstBuilder(RISCV::FCVT_D_W).addReg(Reg).addReg(ScratchIntReg));
+  Instrs.push_back(MCInstBuilder(RISCV::FCVT_D_W)
+                       .addReg(Reg)
+                       .addReg(ScratchIntReg)
+                       .addImm(7));
   return Instrs;
 }
 

``````````

</details>


https://github.com/llvm/llvm-project/pull/149989


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