[llvm] [AMDGPU] Add post-RA scheduling direction control via target features (PR #147708)
Harrison Hao via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 22 02:13:41 PDT 2025
https://github.com/harrisonGPU updated https://github.com/llvm/llvm-project/pull/147708
>From 7fd17069fe63502f00e0b1dc0098dae49e6e4852 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Wed, 9 Jul 2025 17:46:23 +0800
Subject: [PATCH 1/7] [AMDGPU] Support function attribute to override postRA
scheduling direction
---
llvm/include/llvm/CodeGen/MachineScheduler.h | 1 +
llvm/lib/CodeGen/MachineScheduler.cpp | 2 +-
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 17 +++++++++++++++++
3 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h
index efda7eb8ffc8d..dbb7810791e52 100644
--- a/llvm/include/llvm/CodeGen/MachineScheduler.h
+++ b/llvm/include/llvm/CodeGen/MachineScheduler.h
@@ -116,6 +116,7 @@ enum Direction {
} // namespace MISched
LLVM_ABI extern cl::opt<MISched::Direction> PreRADirection;
+LLVM_ABI extern cl::opt<MISched::Direction> PostRADirection;
LLVM_ABI extern cl::opt<bool> VerifyScheduling;
#ifndef NDEBUG
extern cl::opt<bool> ViewMISchedDAGs;
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 9d5c39ce7ae76..183b8d5f0714e 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -190,7 +190,7 @@ cl::opt<MISched::Direction> PreRADirection(
clEnumValN(MISched::Bidirectional, "bidirectional",
"Force bidirectional pre reg-alloc list scheduling")));
-static cl::opt<MISched::Direction> PostRADirection(
+cl::opt<MISched::Direction> PostRADirection(
"misched-postra-direction", cl::Hidden,
cl::desc("Post reg-alloc list scheduling direction"),
cl::init(MISched::Unspecified),
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index c865082a1dcea..65e77cb543a1e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1147,6 +1147,23 @@ GCNTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
ScheduleDAGInstrs *
GCNTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
+ Attribute PostRADirectionAttr =
+ C->MF->getFunction().getFnAttribute("misched-postra-direction");
+
+ if (PostRADirectionAttr.isValid()) {
+ StringRef PostRADirectionStr = PostRADirectionAttr.getValueAsString();
+ if (PostRADirectionStr == "topdown")
+ PostRADirection = MISched::TopDown;
+ else if (PostRADirectionStr == "bottomup")
+ PostRADirection = MISched::BottomUp;
+ else if (PostRADirectionStr == "bidirectional")
+ PostRADirection = MISched::Bidirectional;
+ else
+ report_fatal_error(
+ Twine("invalid value for 'misched-postra-direction' attribute: ") +
+ PostRADirectionStr);
+ }
+
ScheduleDAGMI *DAG =
new GCNPostScheduleDAGMILive(C, std::make_unique<PostGenericScheduler>(C),
/*RemoveKillFlags=*/true);
>From 0abc3d8ec3c89ba0ae9c177b5ad2740dde78c5ac Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Sun, 13 Jul 2025 20:54:37 +0800
Subject: [PATCH 2/7] [AMDGPU] Add a new attr and lit test.
---
llvm/lib/CodeGen/MachineScheduler.cpp | 19 ++++++++++
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 19 +++++++---
.../CodeGen/AMDGPU/postra-sched-attribute.ll | 38 +++++++++++++++++++
3 files changed, 71 insertions(+), 5 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 183b8d5f0714e..4be575fe069c3 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -4336,6 +4336,25 @@ void PostGenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
RegionPolicy.OnlyTopDown = false;
}
+ LLVM_DEBUG({
+ const char *DirStr = "default";
+ switch (PostRADirection) {
+ case MISched::TopDown:
+ DirStr = "topdown";
+ break;
+ case MISched::BottomUp:
+ DirStr = "bottomup";
+ break;
+ case MISched::Bidirectional:
+ DirStr = "bidirectional";
+ break;
+ default:;
+ }
+
+ dbgs() << "Post-MI-sched direction (" << MF.getName() << "): " << DirStr
+ << '\n';
+ });
+
BotIdx = NumRegionInstrs - 1;
this->NumRegionInstrs = NumRegionInstrs;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 65e77cb543a1e..2e6b0d4043863 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -458,6 +458,11 @@ static cl::opt<std::string>
cl::desc("Select custom AMDGPU scheduling strategy."),
cl::Hidden, cl::init(""));
+static cl::opt<std::string>
+ AMDGPUPostRADirection("amdgpu-post-ra-direction",
+ cl::desc("Select custom AMDGPU postRA direction."),
+ cl::Hidden, cl::init(""));
+
static cl::opt<bool> EnableRewritePartialRegUses(
"amdgpu-enable-rewrite-partial-reg-uses",
cl::desc("Enable rewrite partial reg uses pass"), cl::init(true),
@@ -1148,7 +1153,7 @@ GCNTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
ScheduleDAGInstrs *
GCNTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
Attribute PostRADirectionAttr =
- C->MF->getFunction().getFnAttribute("misched-postra-direction");
+ C->MF->getFunction().getFnAttribute("amdgpu-post-ra-direction");
if (PostRADirectionAttr.isValid()) {
StringRef PostRADirectionStr = PostRADirectionAttr.getValueAsString();
@@ -1158,10 +1163,14 @@ GCNTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
PostRADirection = MISched::BottomUp;
else if (PostRADirectionStr == "bidirectional")
PostRADirection = MISched::Bidirectional;
- else
- report_fatal_error(
- Twine("invalid value for 'misched-postra-direction' attribute: ") +
- PostRADirectionStr);
+ else {
+ PostRADirection = MISched::Unspecified;
+ DiagnosticInfoOptimizationFailure Diag(
+ C->MF->getFunction(), C->MF->getFunction().getSubprogram(),
+ Twine("invalid value for postRa direction attribute: '") +
+ PostRADirectionStr);
+ C->MF->getFunction().getContext().diagnose(Diag);
+ }
}
ScheduleDAGMI *DAG =
diff --git a/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll b/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll
new file mode 100644
index 0000000000000..7d9422d81c129
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll
@@ -0,0 +1,38 @@
+; REQUIRES: asserts
+
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -debug-only=machine-scheduler < %s 2>&1 | FileCheck %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s 2>&1 | FileCheck -check-prefixes=WARNING %s
+
+; CHECK-LABEL: {{^}}postra-sched-topdown:
+; CHECK: Post-MI-sched direction (postra-sched-topdown): topdown
+define float @postra-sched-topdown(float %input) nounwind #0 {
+ %x = fadd float %input, 1.000000e+00
+ ret float %x
+}
+
+; CHECK-LABEL: {{^}}postra-sched-bottomup:
+; CHECK: Post-MI-sched direction (postra-sched-bottomup): bottomup
+define float @postra-sched-bottomup(float %input) nounwind #1 {
+ %x = fsub float %input, 1.000000e+00
+ ret float %x
+}
+
+; CHECK-LABEL: {{^}}postra-sched-bidirectional:
+; CHECK: Post-MI-sched direction (postra-sched-bidirectional): bidirectional
+define float @postra-sched-bidirectional(float %input) nounwind #2 {
+ %x = fadd float %input, 1.000000e+00
+ ret float %x
+}
+
+; CHECK-LABEL: {{^}}postra-sched-warning:
+; CHECK: Post-MI-sched direction (postra-sched-warning): default
+; WARNING: invalid value for postRa direction attribute
+define float @postra-sched-warning(float %input) nounwind #3 {
+ %x = fsub float %input, 1.000000e+00
+ ret float %x
+}
+
+attributes #0 = { alwaysinline nounwind memory(readwrite) "amdgpu-post-ra-direction"="topdown"}
+attributes #1 = { alwaysinline nounwind memory(readwrite) "amdgpu-post-ra-direction"="bottomup"}
+attributes #2 = { alwaysinline nounwind memory(readwrite) "amdgpu-post-ra-direction"="bidirectional"}
+attributes #3 = { alwaysinline nounwind memory(readwrite) "amdgpu-post-ra-direction"="warning"}
>From c312b16f953d3daa0c1ccc7c10fab831a12888b8 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Mon, 14 Jul 2025 09:51:36 +0800
Subject: [PATCH 3/7] [AMDGPU] Remove other att.
---
llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll b/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll
index 7d9422d81c129..c6f63f3b4a1b3 100644
--- a/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll
+++ b/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll
@@ -32,7 +32,7 @@ define float @postra-sched-warning(float %input) nounwind #3 {
ret float %x
}
-attributes #0 = { alwaysinline nounwind memory(readwrite) "amdgpu-post-ra-direction"="topdown"}
-attributes #1 = { alwaysinline nounwind memory(readwrite) "amdgpu-post-ra-direction"="bottomup"}
-attributes #2 = { alwaysinline nounwind memory(readwrite) "amdgpu-post-ra-direction"="bidirectional"}
-attributes #3 = { alwaysinline nounwind memory(readwrite) "amdgpu-post-ra-direction"="warning"}
+attributes #0 = {"amdgpu-post-ra-direction"="topdown"}
+attributes #1 = {"amdgpu-post-ra-direction"="bottomup"}
+attributes #2 = {"amdgpu-post-ra-direction"="bidirectional"}
+attributes #3 = {"amdgpu-post-ra-direction"="warning"}
>From b27b075f8de0fb880c9010e9bf1def75361a2d77 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Tue, 15 Jul 2025 13:48:18 +0800
Subject: [PATCH 4/7] [AMDGPU]
---
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 38 ++++++++++---------
1 file changed, 20 insertions(+), 18 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 2e6b0d4043863..120375e5c5317 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1152,24 +1152,26 @@ GCNTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
ScheduleDAGInstrs *
GCNTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
- Attribute PostRADirectionAttr =
- C->MF->getFunction().getFnAttribute("amdgpu-post-ra-direction");
-
- if (PostRADirectionAttr.isValid()) {
- StringRef PostRADirectionStr = PostRADirectionAttr.getValueAsString();
- if (PostRADirectionStr == "topdown")
- PostRADirection = MISched::TopDown;
- else if (PostRADirectionStr == "bottomup")
- PostRADirection = MISched::BottomUp;
- else if (PostRADirectionStr == "bidirectional")
- PostRADirection = MISched::Bidirectional;
- else {
- PostRADirection = MISched::Unspecified;
- DiagnosticInfoOptimizationFailure Diag(
- C->MF->getFunction(), C->MF->getFunction().getSubprogram(),
- Twine("invalid value for postRa direction attribute: '") +
- PostRADirectionStr);
- C->MF->getFunction().getContext().diagnose(Diag);
+ if (PostRADirection.getNumOccurrences() == 0) {
+ Attribute PostRADirectionAttr =
+ C->MF->getFunction().getFnAttribute("amdgpu-post-ra-direction");
+
+ if (PostRADirectionAttr.isValid()) {
+ StringRef PostRADirectionStr = PostRADirectionAttr.getValueAsString();
+ if (PostRADirectionStr == "topdown")
+ PostRADirection = MISched::TopDown;
+ else if (PostRADirectionStr == "bottomup")
+ PostRADirection = MISched::BottomUp;
+ else if (PostRADirectionStr == "bidirectional")
+ PostRADirection = MISched::Bidirectional;
+ else {
+ PostRADirection = MISched::Unspecified;
+ DiagnosticInfoOptimizationFailure Diag(
+ C->MF->getFunction(), C->MF->getFunction().getSubprogram(),
+ Twine("invalid value for postRa direction attribute: '") +
+ PostRADirectionStr);
+ C->MF->getFunction().getContext().diagnose(Diag);
+ }
}
}
>From 5443de8aab3529f361123ff4d0e6079d3d32f4fe Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Tue, 15 Jul 2025 20:00:37 +0800
Subject: [PATCH 5/7] [AMDGPU] Add post-RA scheduling direction control via
target features
---
llvm/include/llvm/CodeGen/MachineScheduler.h | 1 -
llvm/lib/CodeGen/MachineScheduler.cpp | 21 +---------
llvm/lib/Target/AMDGPU/AMDGPUFeatures.td | 21 ++++++++++
llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h | 6 +++
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 28 --------------
llvm/lib/Target/AMDGPU/GCNSubtarget.cpp | 34 +++++++++++++++++
llvm/lib/Target/AMDGPU/GCNSubtarget.h | 3 ++
.../CodeGen/AMDGPU/postra-sched-attribute.ll | 38 -------------------
.../AMDGPU/postra-sched-target-features.ll | 25 ++++++++++++
9 files changed, 90 insertions(+), 87 deletions(-)
delete mode 100644 llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll
create mode 100644 llvm/test/CodeGen/AMDGPU/postra-sched-target-features.ll
diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h
index dbb7810791e52..efda7eb8ffc8d 100644
--- a/llvm/include/llvm/CodeGen/MachineScheduler.h
+++ b/llvm/include/llvm/CodeGen/MachineScheduler.h
@@ -116,7 +116,6 @@ enum Direction {
} // namespace MISched
LLVM_ABI extern cl::opt<MISched::Direction> PreRADirection;
-LLVM_ABI extern cl::opt<MISched::Direction> PostRADirection;
LLVM_ABI extern cl::opt<bool> VerifyScheduling;
#ifndef NDEBUG
extern cl::opt<bool> ViewMISchedDAGs;
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 4be575fe069c3..9d5c39ce7ae76 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -190,7 +190,7 @@ cl::opt<MISched::Direction> PreRADirection(
clEnumValN(MISched::Bidirectional, "bidirectional",
"Force bidirectional pre reg-alloc list scheduling")));
-cl::opt<MISched::Direction> PostRADirection(
+static cl::opt<MISched::Direction> PostRADirection(
"misched-postra-direction", cl::Hidden,
cl::desc("Post reg-alloc list scheduling direction"),
cl::init(MISched::Unspecified),
@@ -4336,25 +4336,6 @@ void PostGenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
RegionPolicy.OnlyTopDown = false;
}
- LLVM_DEBUG({
- const char *DirStr = "default";
- switch (PostRADirection) {
- case MISched::TopDown:
- DirStr = "topdown";
- break;
- case MISched::BottomUp:
- DirStr = "bottomup";
- break;
- case MISched::Bidirectional:
- DirStr = "bidirectional";
- break;
- default:;
- }
-
- dbgs() << "Post-MI-sched direction (" << MF.getName() << "): " << DirStr
- << '\n';
- });
-
BotIdx = NumRegionInstrs - 1;
this->NumRegionInstrs = NumRegionInstrs;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td b/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td
index 74d1faeb6f545..870144f43b993 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td
@@ -6,6 +6,10 @@
//
//===----------------------------------------------------------------------===//
+defvar TopDown = [{ MISched::TopDown }];
+defvar BottomUp = [{ MISched::BottomUp }];
+defvar Bidirectional = [{ MISched::Bidirectional }];
+
def FeatureFP64 : SubtargetFeature<"fp64",
"FP64",
"true",
@@ -54,3 +58,20 @@ def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
"Enable promote alloca pass"
>;
+def FeaturePostRATopDown : SubtargetFeature <"postra-top-down",
+ "PostRASchedDirection",
+ TopDown,
+ "Force Post-RA scheduler to run top-down"
+>;
+
+def FeaturePostRABottomUp : SubtargetFeature <"postra-bottom-up",
+ "PostRASchedDirection",
+ BottomUp,
+ "Force Post-RA scheduler to run bottom-up"
+>;
+
+def FeaturePostRABidirectional : SubtargetFeature <"postra-bidirectional",
+ "PostRASchedDirection",
+ Bidirectional,
+ "Force Post-RA scheduler to run bidirectionally"
+>;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
index 1e44be8e47201..3b1b154abdeb9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
@@ -15,6 +15,7 @@
#define LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
#include "llvm/ADT/SmallVector.h"
+#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/Support/Alignment.h"
#include "llvm/TargetParser/Triple.h"
@@ -79,6 +80,7 @@ class AMDGPUSubtarget {
unsigned LocalMemorySize = 0;
unsigned AddressableLocalMemorySize = 0;
char WavefrontSizeLog2 = 0;
+ MISched::Direction PostRASchedDirection = MISched::TopDown;
public:
AMDGPUSubtarget(Triple TT);
@@ -379,6 +381,10 @@ class AMDGPUSubtarget {
AMDGPUDwarfFlavour getAMDGPUDwarfFlavour() const;
virtual ~AMDGPUSubtarget() = default;
+
+ MISched::Direction getPostRASchedDirection() const {
+ return PostRASchedDirection;
+ }
};
} // end namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 120375e5c5317..c865082a1dcea 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -458,11 +458,6 @@ static cl::opt<std::string>
cl::desc("Select custom AMDGPU scheduling strategy."),
cl::Hidden, cl::init(""));
-static cl::opt<std::string>
- AMDGPUPostRADirection("amdgpu-post-ra-direction",
- cl::desc("Select custom AMDGPU postRA direction."),
- cl::Hidden, cl::init(""));
-
static cl::opt<bool> EnableRewritePartialRegUses(
"amdgpu-enable-rewrite-partial-reg-uses",
cl::desc("Enable rewrite partial reg uses pass"), cl::init(true),
@@ -1152,29 +1147,6 @@ GCNTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
ScheduleDAGInstrs *
GCNTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
- if (PostRADirection.getNumOccurrences() == 0) {
- Attribute PostRADirectionAttr =
- C->MF->getFunction().getFnAttribute("amdgpu-post-ra-direction");
-
- if (PostRADirectionAttr.isValid()) {
- StringRef PostRADirectionStr = PostRADirectionAttr.getValueAsString();
- if (PostRADirectionStr == "topdown")
- PostRADirection = MISched::TopDown;
- else if (PostRADirectionStr == "bottomup")
- PostRADirection = MISched::BottomUp;
- else if (PostRADirectionStr == "bidirectional")
- PostRADirection = MISched::Bidirectional;
- else {
- PostRADirection = MISched::Unspecified;
- DiagnosticInfoOptimizationFailure Diag(
- C->MF->getFunction(), C->MF->getFunction().getSubprogram(),
- Twine("invalid value for postRa direction attribute: '") +
- PostRADirectionStr);
- C->MF->getFunction().getContext().diagnose(Diag);
- }
- }
- }
-
ScheduleDAGMI *DAG =
new GCNPostScheduleDAGMILive(C, std::make_unique<PostGenericScheduler>(C),
/*RemoveKillFlags=*/true);
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
index 9a2bab108232d..9a8c4eebed64f 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
@@ -340,6 +340,40 @@ void GCNSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
Policy.ShouldTrackLaneMasks = true;
}
+void GCNSubtarget::overridePostRASchedPolicy(MachineSchedPolicy &Policy,
+ unsigned NumRegionInstrs) const {
+ switch (getPostRASchedDirection()) {
+ case MISched::TopDown:
+ Policy.OnlyTopDown = true;
+ Policy.OnlyBottomUp = false;
+ break;
+ case MISched::BottomUp:
+ Policy.OnlyTopDown = false;
+ Policy.OnlyBottomUp = true;
+ break;
+ case MISched::Bidirectional:
+ default:
+ Policy.OnlyTopDown = false;
+ Policy.OnlyBottomUp = false;
+ break;
+ }
+
+ LLVM_DEBUG({
+ const char *DirStr = "topdown";
+ switch (getPostRASchedDirection()) {
+ case MISched::BottomUp:
+ DirStr = "bottomup";
+ break;
+ case MISched::Bidirectional:
+ DirStr = "bidirectional";
+ break;
+ default:
+ break;
+ }
+ dbgs() << "Post-MI-sched direction: " << DirStr << '\n';
+ });
+}
+
void GCNSubtarget::mirFileLoaded(MachineFunction &MF) const {
if (isWave32()) {
// Fix implicit $vcc operands after MIParser has verified that they match
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index 407d79a30599b..68aa00a992a51 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -1024,6 +1024,9 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
void overrideSchedPolicy(MachineSchedPolicy &Policy,
const SchedRegion &Region) const override;
+ void overridePostRASchedPolicy(MachineSchedPolicy &Policy,
+ unsigned NumRegionInstrs) const override;
+
void mirFileLoaded(MachineFunction &MF) const override;
unsigned getMaxNumUserSGPRs() const {
diff --git a/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll b/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll
deleted file mode 100644
index c6f63f3b4a1b3..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll
+++ /dev/null
@@ -1,38 +0,0 @@
-; REQUIRES: asserts
-
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -debug-only=machine-scheduler < %s 2>&1 | FileCheck %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s 2>&1 | FileCheck -check-prefixes=WARNING %s
-
-; CHECK-LABEL: {{^}}postra-sched-topdown:
-; CHECK: Post-MI-sched direction (postra-sched-topdown): topdown
-define float @postra-sched-topdown(float %input) nounwind #0 {
- %x = fadd float %input, 1.000000e+00
- ret float %x
-}
-
-; CHECK-LABEL: {{^}}postra-sched-bottomup:
-; CHECK: Post-MI-sched direction (postra-sched-bottomup): bottomup
-define float @postra-sched-bottomup(float %input) nounwind #1 {
- %x = fsub float %input, 1.000000e+00
- ret float %x
-}
-
-; CHECK-LABEL: {{^}}postra-sched-bidirectional:
-; CHECK: Post-MI-sched direction (postra-sched-bidirectional): bidirectional
-define float @postra-sched-bidirectional(float %input) nounwind #2 {
- %x = fadd float %input, 1.000000e+00
- ret float %x
-}
-
-; CHECK-LABEL: {{^}}postra-sched-warning:
-; CHECK: Post-MI-sched direction (postra-sched-warning): default
-; WARNING: invalid value for postRa direction attribute
-define float @postra-sched-warning(float %input) nounwind #3 {
- %x = fsub float %input, 1.000000e+00
- ret float %x
-}
-
-attributes #0 = {"amdgpu-post-ra-direction"="topdown"}
-attributes #1 = {"amdgpu-post-ra-direction"="bottomup"}
-attributes #2 = {"amdgpu-post-ra-direction"="bidirectional"}
-attributes #3 = {"amdgpu-post-ra-direction"="warning"}
diff --git a/llvm/test/CodeGen/AMDGPU/postra-sched-target-features.ll b/llvm/test/CodeGen/AMDGPU/postra-sched-target-features.ll
new file mode 100644
index 0000000000000..339fbe4159db4
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/postra-sched-target-features.ll
@@ -0,0 +1,25 @@
+; REQUIRES: asserts
+
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -debug-only=gcn-subtarget < %s 2>&1 | FileCheck %s
+
+; CHECK: Post-MI-sched direction: topdown
+define float @postra-sched-topdown(float %input) nounwind #0 {
+ %x = fadd float %input, 1.000000e+00
+ ret float %x
+}
+
+; CHECK: Post-MI-sched direction: bottomup
+define float @postra-sched-bottomup(float %input) nounwind #1 {
+ %x = fsub float %input, 1.000000e+00
+ ret float %x
+}
+
+; CHECK: Post-MI-sched direction: bidirectional
+define float @postra-sched-bidirectional(float %input) nounwind #2 {
+ %x = fadd float %input, 1.000000e+00
+ ret float %x
+}
+
+attributes #0 = { "target-features"="+postra-top-down" }
+attributes #1 = { "target-features"="+postra-bottom-up" }
+attributes #2 = { "target-features"="+postra-bidirectional" }
>From d45f50ef64524d414a72ae4566711d03f1daaa9f Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Thu, 17 Jul 2025 17:44:17 +0800
Subject: [PATCH 6/7] [AMDGPU]
---
.../llvm/CodeGen/TargetSubtargetInfo.h | 1 +
llvm/lib/Target/AMDGPU/GCNSubtarget.cpp | 79 +++++++++++++------
llvm/lib/Target/AMDGPU/GCNSubtarget.h | 3 +-
3 files changed, 58 insertions(+), 25 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
index a8c7a8aff83cf..3be7c6a45298c 100644
--- a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
@@ -16,6 +16,7 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MacroFusion.h"
#include "llvm/CodeGen/PBQPRAConstraint.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
index 9a8c4eebed64f..b517556bdd0c7 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
@@ -52,6 +52,11 @@ static cl::opt<unsigned>
cl::desc("Number of addresses from which to enable MIMG NSA."),
cl::init(2), cl::Hidden);
+static cl::opt<std::string>
+ AMDGPUPostRADirection("amdgpu-post-ra-direction",
+ cl::desc("Select custom AMDGPU postRA direction."),
+ cl::Hidden, cl::init(""));
+
GCNSubtarget::~GCNSubtarget() = default;
GCNSubtarget &GCNSubtarget::initializeSubtargetDependencies(const Triple &TT,
@@ -341,37 +346,63 @@ void GCNSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
}
void GCNSubtarget::overridePostRASchedPolicy(MachineSchedPolicy &Policy,
- unsigned NumRegionInstrs) const {
- switch (getPostRASchedDirection()) {
- case MISched::TopDown:
+ const MachineBasicBlock &MBB,
+ unsigned NumRegionInstr) const {
+ const Function &F = MBB.getParent()->getFunction();
+ Attribute PostRADirectionAttr = F.getFnAttribute("amdgpu-post-ra-direction");
+ if (!PostRADirectionAttr.isValid())
+ return;
+
+ StringRef PostRADirectionStr = PostRADirectionAttr.getValueAsString();
+ if (PostRADirectionStr == "topdown") {
Policy.OnlyTopDown = true;
Policy.OnlyBottomUp = false;
- break;
- case MISched::BottomUp:
+ } else if (PostRADirectionStr == "bottomup") {
Policy.OnlyTopDown = false;
Policy.OnlyBottomUp = true;
- break;
- case MISched::Bidirectional:
- default:
+ } else if (PostRADirectionStr == "bidirectional") {
Policy.OnlyTopDown = false;
Policy.OnlyBottomUp = false;
- break;
+ } else {
+ DiagnosticInfoOptimizationFailure Diag(
+ F, F.getSubprogram(),
+ Twine("invalid value for postRa direction attribute: '") +
+ PostRADirectionStr);
+ F.getContext().diagnose(Diag);
}
-
- LLVM_DEBUG({
- const char *DirStr = "topdown";
- switch (getPostRASchedDirection()) {
- case MISched::BottomUp:
- DirStr = "bottomup";
- break;
- case MISched::Bidirectional:
- DirStr = "bidirectional";
- break;
- default:
- break;
- }
- dbgs() << "Post-MI-sched direction: " << DirStr << '\n';
- });
+ // }
+
+ // switch (getPostRASchedDirection()) {
+ // case MISched::TopDown:
+ // Policy.OnlyTopDown = true;
+ // Policy.OnlyBottomUp = false;
+ // break;
+ // case MISched::BottomUp:
+ // Policy.OnlyTopDown = false;
+ // Policy.OnlyBottomUp = true;
+ // break;
+ // case MISched::Bidirectional:
+ // Policy.OnlyTopDown = false;
+ // Policy.OnlyBottomUp = false;
+ // break;
+ // default:
+ // break;
+ // }
+
+ // LLVM_DEBUG({
+ // const char *DirStr = "topdown";
+ // switch (getPostRASchedDirection()) {
+ // case MISched::BottomUp:
+ // DirStr = "bottomup";
+ // break;
+ // case MISched::Bidirectional:
+ // DirStr = "bidirectional";
+ // break;
+ // default:
+ // break;
+ // }
+ // dbgs() << "Post-MI-sched direction: " << DirStr << '\n';
+ // });
}
void GCNSubtarget::mirFileLoaded(MachineFunction &MF) const {
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index 68aa00a992a51..3bd5283d90511 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -1025,7 +1025,8 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
const SchedRegion &Region) const override;
void overridePostRASchedPolicy(MachineSchedPolicy &Policy,
- unsigned NumRegionInstrs) const override;
+ const MachineBasicBlock &MBB,
+ unsigned NumRegionInstr) const override;
void mirFileLoaded(MachineFunction &MF) const override;
>From bb7a6ebeb4c59ac94871f19add0b4de172d25c06 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Tue, 22 Jul 2025 17:12:29 +0800
Subject: [PATCH 7/7] [AMDGPU] Use function attribute for post-ra
---
.../llvm/CodeGen/TargetSubtargetInfo.h | 1 -
llvm/lib/Target/AMDGPU/AMDGPUFeatures.td | 22 --------
llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h | 6 ---
llvm/lib/Target/AMDGPU/GCNSubtarget.cpp | 51 ++++++-------------
llvm/lib/Target/AMDGPU/GCNSubtarget.h | 3 +-
.../CodeGen/AMDGPU/postra-sched-attribute.ll | 34 +++++++++++++
.../AMDGPU/postra-sched-target-features.ll | 25 ---------
7 files changed, 50 insertions(+), 92 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll
delete mode 100644 llvm/test/CodeGen/AMDGPU/postra-sched-target-features.ll
diff --git a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
index 3be7c6a45298c..a8c7a8aff83cf 100644
--- a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
@@ -16,7 +16,6 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
-#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MacroFusion.h"
#include "llvm/CodeGen/PBQPRAConstraint.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td b/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td
index 870144f43b993..bdc6073889bf3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td
@@ -6,10 +6,6 @@
//
//===----------------------------------------------------------------------===//
-defvar TopDown = [{ MISched::TopDown }];
-defvar BottomUp = [{ MISched::BottomUp }];
-defvar Bidirectional = [{ MISched::Bidirectional }];
-
def FeatureFP64 : SubtargetFeature<"fp64",
"FP64",
"true",
@@ -57,21 +53,3 @@ def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
"true",
"Enable promote alloca pass"
>;
-
-def FeaturePostRATopDown : SubtargetFeature <"postra-top-down",
- "PostRASchedDirection",
- TopDown,
- "Force Post-RA scheduler to run top-down"
->;
-
-def FeaturePostRABottomUp : SubtargetFeature <"postra-bottom-up",
- "PostRASchedDirection",
- BottomUp,
- "Force Post-RA scheduler to run bottom-up"
->;
-
-def FeaturePostRABidirectional : SubtargetFeature <"postra-bidirectional",
- "PostRASchedDirection",
- Bidirectional,
- "Force Post-RA scheduler to run bidirectionally"
->;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
index 3b1b154abdeb9..1e44be8e47201 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
@@ -15,7 +15,6 @@
#define LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
#include "llvm/ADT/SmallVector.h"
-#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/Support/Alignment.h"
#include "llvm/TargetParser/Triple.h"
@@ -80,7 +79,6 @@ class AMDGPUSubtarget {
unsigned LocalMemorySize = 0;
unsigned AddressableLocalMemorySize = 0;
char WavefrontSizeLog2 = 0;
- MISched::Direction PostRASchedDirection = MISched::TopDown;
public:
AMDGPUSubtarget(Triple TT);
@@ -381,10 +379,6 @@ class AMDGPUSubtarget {
AMDGPUDwarfFlavour getAMDGPUDwarfFlavour() const;
virtual ~AMDGPUSubtarget() = default;
-
- MISched::Direction getPostRASchedDirection() const {
- return PostRASchedDirection;
- }
};
} // end namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
index b517556bdd0c7..85ef987d601d7 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
@@ -346,9 +346,8 @@ void GCNSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
}
void GCNSubtarget::overridePostRASchedPolicy(MachineSchedPolicy &Policy,
- const MachineBasicBlock &MBB,
- unsigned NumRegionInstr) const {
- const Function &F = MBB.getParent()->getFunction();
+ const SchedRegion &Region) const {
+ const Function &F = Region.RegionBegin->getMF()->getFunction();
Attribute PostRADirectionAttr = F.getFnAttribute("amdgpu-post-ra-direction");
if (!PostRADirectionAttr.isValid())
return;
@@ -370,39 +369,19 @@ void GCNSubtarget::overridePostRASchedPolicy(MachineSchedPolicy &Policy,
PostRADirectionStr);
F.getContext().diagnose(Diag);
}
- // }
-
- // switch (getPostRASchedDirection()) {
- // case MISched::TopDown:
- // Policy.OnlyTopDown = true;
- // Policy.OnlyBottomUp = false;
- // break;
- // case MISched::BottomUp:
- // Policy.OnlyTopDown = false;
- // Policy.OnlyBottomUp = true;
- // break;
- // case MISched::Bidirectional:
- // Policy.OnlyTopDown = false;
- // Policy.OnlyBottomUp = false;
- // break;
- // default:
- // break;
- // }
-
- // LLVM_DEBUG({
- // const char *DirStr = "topdown";
- // switch (getPostRASchedDirection()) {
- // case MISched::BottomUp:
- // DirStr = "bottomup";
- // break;
- // case MISched::Bidirectional:
- // DirStr = "bidirectional";
- // break;
- // default:
- // break;
- // }
- // dbgs() << "Post-MI-sched direction: " << DirStr << '\n';
- // });
+
+ LLVM_DEBUG({
+ const char *DirStr = "default";
+ if (Policy.OnlyTopDown && !Policy.OnlyBottomUp)
+ DirStr = "topdown";
+ else if (!Policy.OnlyTopDown && Policy.OnlyBottomUp)
+ DirStr = "bottomup";
+ else if (!Policy.OnlyTopDown && !Policy.OnlyBottomUp)
+ DirStr = "bidirectional";
+
+ dbgs() << "Post-MI-sched direction (" << F.getName() << "): " << DirStr
+ << '\n';
+ });
}
void GCNSubtarget::mirFileLoaded(MachineFunction &MF) const {
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index 3bd5283d90511..8cdbd47f0bb34 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -1025,8 +1025,7 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
const SchedRegion &Region) const override;
void overridePostRASchedPolicy(MachineSchedPolicy &Policy,
- const MachineBasicBlock &MBB,
- unsigned NumRegionInstr) const override;
+ const SchedRegion &Region) const override;
void mirFileLoaded(MachineFunction &MF) const override;
diff --git a/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll b/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll
new file mode 100644
index 0000000000000..4d517fc640945
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll
@@ -0,0 +1,34 @@
+; REQUIRES: asserts
+
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -debug-only=gcn-subtarget < %s 2>&1 | FileCheck %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s 2>&1 | FileCheck -check-prefixes=WARNING %s
+
+; CHECK: Post-MI-sched direction (postra-sched-topdown): topdown
+define float @postra-sched-topdown(float %input) nounwind #0 {
+ %x = fadd float %input, 1.000000e+00
+ ret float %x
+}
+
+; CHECK: Post-MI-sched direction (postra-sched-bottomup): bottomup
+define float @postra-sched-bottomup(float %input) nounwind #1 {
+ %x = fsub float %input, 1.000000e+00
+ ret float %x
+}
+
+; CHECK: Post-MI-sched direction (postra-sched-bidirectional): bidirectional
+define float @postra-sched-bidirectional(float %input) nounwind #2 {
+ %x = fadd float %input, 1.000000e+00
+ ret float %x
+}
+
+; CHECK: Post-MI-sched direction (postra-sched-warning): topdown
+; WARNING: invalid value for postRa direction attribute
+define float @postra-sched-warning(float %input) nounwind #3 {
+ %x = fsub float %input, 1.000000e+00
+ ret float %x
+}
+
+attributes #0 = {"amdgpu-post-ra-direction"="topdown"}
+attributes #1 = {"amdgpu-post-ra-direction"="bottomup"}
+attributes #2 = {"amdgpu-post-ra-direction"="bidirectional"}
+attributes #3 = {"amdgpu-post-ra-direction"="warning"}
diff --git a/llvm/test/CodeGen/AMDGPU/postra-sched-target-features.ll b/llvm/test/CodeGen/AMDGPU/postra-sched-target-features.ll
deleted file mode 100644
index 339fbe4159db4..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/postra-sched-target-features.ll
+++ /dev/null
@@ -1,25 +0,0 @@
-; REQUIRES: asserts
-
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -debug-only=gcn-subtarget < %s 2>&1 | FileCheck %s
-
-; CHECK: Post-MI-sched direction: topdown
-define float @postra-sched-topdown(float %input) nounwind #0 {
- %x = fadd float %input, 1.000000e+00
- ret float %x
-}
-
-; CHECK: Post-MI-sched direction: bottomup
-define float @postra-sched-bottomup(float %input) nounwind #1 {
- %x = fsub float %input, 1.000000e+00
- ret float %x
-}
-
-; CHECK: Post-MI-sched direction: bidirectional
-define float @postra-sched-bidirectional(float %input) nounwind #2 {
- %x = fadd float %input, 1.000000e+00
- ret float %x
-}
-
-attributes #0 = { "target-features"="+postra-top-down" }
-attributes #1 = { "target-features"="+postra-bottom-up" }
-attributes #2 = { "target-features"="+postra-bidirectional" }
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