[llvm] [RISCV] Copy base instruction TSFlags in RVV pseudo TSFlags. NFC (PR #149785)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 22 00:53:07 PDT 2025
https://github.com/lukel97 updated https://github.com/llvm/llvm-project/pull/149785
>From d9473a16b9bb23bef8d1646f2b453c1e3a959c88 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Mon, 21 Jul 2025 17:22:52 +0800
Subject: [PATCH 1/3] [RISCV] Copy base instruction TSFlags in RVV pseudo
TSFlags. NFC
As pointed out in https://github.com/llvm/llvm-project/pull/149704/files#r2218484702, we currently define TSFlags for vector instruction behaviour on the underlying base instruction.
But we normally operate on pseudos, so whenever we want to check the TSFlags it requires a pseudo table lookup to get the base instruction.
This PR copies over these TSFlags to the pseudos' TSFlags so we can avoid the table lookup. To do this I needed to merge Pseudo and RISCVVPseudo so the latter extends the former.
---
.../Target/RISCV/RISCVInstrInfoVPseudos.td | 249 +++++++-----------
llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td | 6 +-
llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td | 10 +-
llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td | 30 +--
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td | 10 +-
llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 6 +-
llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp | 15 +-
7 files changed, 127 insertions(+), 199 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index de9e55beb6a5e..7d3e799bb205f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -543,12 +543,17 @@ defset list<VTypeInfoToWide> AllWidenableBFloatToFloatVectors = {
// This represents the information we need in codegen for each pseudo.
// The definition should be consistent with `struct PseudoInfo` in
// RISCVInstrInfo.h.
-class RISCVVPseudo {
+class RISCVVPseudo<dag outs, dag ins, list<dag> pattern, string opcodestr = "", string argstr = "">
+ : Pseudo<outs, ins, pattern, opcodestr, argstr> {
Pseudo Pseudo = !cast<Pseudo>(NAME); // Used as a key.
Instruction BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
// SEW = 0 is used to denote that the Pseudo is not SEW specific (or unknown).
bits<8> SEW = 0;
bit IncludeInInversePseudoTable = 1;
+
+ // Set common TSFlags in RVInst from the base instruction.
+ let ElementsDependOn = !cast<RVInst>(BaseInstr).ElementsDependOn;
+ let DestEEW = !cast<RVInst>(BaseInstr).DestEEW;
}
// The actual table.
@@ -785,10 +790,9 @@ class GetVTypeMinimalPredicates<VTypeInfo vti> {
class VPseudoUSLoadNoMask<VReg RetClass,
int EEW,
DAGOperand sewop = sew> :
- Pseudo<(outs RetClass:$rd),
+ RISCVVPseudo<(outs RetClass:$rd),
(ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$vl, sewop:$sew,
vec_policy:$policy), []>,
- RISCVVPseudo,
RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
@@ -801,11 +805,10 @@ class VPseudoUSLoadNoMask<VReg RetClass,
class VPseudoUSLoadMask<VReg RetClass,
int EEW> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
+ RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
GPRMemZeroOffset:$rs1,
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo,
RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
@@ -820,10 +823,9 @@ class VPseudoUSLoadMask<VReg RetClass,
class VPseudoUSLoadFFNoMask<VReg RetClass,
int EEW> :
- Pseudo<(outs RetClass:$rd, GPR:$vl),
+ RISCVVPseudo<(outs RetClass:$rd, GPR:$vl),
(ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$avl,
sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo,
RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
@@ -836,11 +838,10 @@ class VPseudoUSLoadFFNoMask<VReg RetClass,
class VPseudoUSLoadFFMask<VReg RetClass,
int EEW> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl),
+ RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl),
(ins GetVRegNoV0<RetClass>.R:$passthru,
GPRMemZeroOffset:$rs1,
VMaskOp:$vm, AVL:$avl, sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo,
RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
@@ -855,10 +856,9 @@ class VPseudoUSLoadFFMask<VReg RetClass,
class VPseudoSLoadNoMask<VReg RetClass,
int EEW> :
- Pseudo<(outs RetClass:$rd),
+ RISCVVPseudo<(outs RetClass:$rd),
(ins RetClass:$dest, GPRMemZeroOffset:$rs1, GPR:$rs2, AVL:$vl,
sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo,
RISCVVLE</*Masked*/0, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
@@ -871,11 +871,10 @@ class VPseudoSLoadNoMask<VReg RetClass,
class VPseudoSLoadMask<VReg RetClass,
int EEW> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
+ RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
GPRMemZeroOffset:$rs1, GPR:$rs2,
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo,
RISCVVLE</*Masked*/1, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
@@ -895,10 +894,9 @@ class VPseudoILoadNoMask<VReg RetClass,
bit Ordered,
bit EarlyClobber,
bits<2> TargetConstraintType = 1> :
- Pseudo<(outs RetClass:$rd),
+ RISCVVPseudo<(outs RetClass:$rd),
(ins RetClass:$dest, GPRMemZeroOffset:$rs1, IdxClass:$rs2, AVL:$vl,
sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo,
RISCVVLX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 1;
let mayStore = 0;
@@ -917,11 +915,10 @@ class VPseudoILoadMask<VReg RetClass,
bit Ordered,
bit EarlyClobber,
bits<2> TargetConstraintType = 1> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
+ RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
GPRMemZeroOffset:$rs1, IdxClass:$rs2,
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo,
RISCVVLX</*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 1;
let mayStore = 0;
@@ -938,9 +935,8 @@ class VPseudoILoadMask<VReg RetClass,
class VPseudoUSStoreNoMask<VReg StClass,
int EEW,
DAGOperand sewop = sew> :
- Pseudo<(outs),
+ RISCVVPseudo<(outs),
(ins StClass:$rd, GPRMemZeroOffset:$rs1, AVL:$vl, sewop:$sew), []>,
- RISCVVPseudo,
RISCVVSE</*Masked*/0, /*Strided*/0, !logtwo(EEW), VLMul> {
let mayLoad = 0;
let mayStore = 1;
@@ -951,10 +947,9 @@ class VPseudoUSStoreNoMask<VReg StClass,
class VPseudoUSStoreMask<VReg StClass,
int EEW> :
- Pseudo<(outs),
+ RISCVVPseudo<(outs),
(ins StClass:$rd, GPRMemZeroOffset:$rs1,
VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
- RISCVVPseudo,
RISCVVSE</*Masked*/1, /*Strided*/0, !logtwo(EEW), VLMul> {
let mayLoad = 0;
let mayStore = 1;
@@ -966,10 +961,9 @@ class VPseudoUSStoreMask<VReg StClass,
class VPseudoSStoreNoMask<VReg StClass,
int EEW> :
- Pseudo<(outs),
+ RISCVVPseudo<(outs),
(ins StClass:$rd, GPRMemZeroOffset:$rs1, GPR:$rs2,
AVL:$vl, sew:$sew), []>,
- RISCVVPseudo,
RISCVVSE</*Masked*/0, /*Strided*/1, !logtwo(EEW), VLMul> {
let mayLoad = 0;
let mayStore = 1;
@@ -980,10 +974,9 @@ class VPseudoSStoreNoMask<VReg StClass,
class VPseudoSStoreMask<VReg StClass,
int EEW> :
- Pseudo<(outs),
+ RISCVVPseudo<(outs),
(ins StClass:$rd, GPRMemZeroOffset:$rs1, GPR:$rs2,
VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
- RISCVVPseudo,
RISCVVSE</*Masked*/1, /*Strided*/1, !logtwo(EEW), VLMul> {
let mayLoad = 0;
let mayStore = 1;
@@ -994,10 +987,9 @@ class VPseudoSStoreMask<VReg StClass,
}
class VPseudoNullaryNoMask<VReg RegClass> :
- Pseudo<(outs RegClass:$rd),
+ RISCVVPseudo<(outs RegClass:$rd),
(ins RegClass:$passthru,
- AVL:$vl, sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo {
+ AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1008,10 +1000,9 @@ class VPseudoNullaryNoMask<VReg RegClass> :
}
class VPseudoNullaryMask<VReg RegClass> :
- Pseudo<(outs GetVRegNoV0<RegClass>.R:$rd),
+ RISCVVPseudo<(outs GetVRegNoV0<RegClass>.R:$rd),
(ins GetVRegNoV0<RegClass>.R:$passthru,
- VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo {
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1026,8 +1017,7 @@ class VPseudoNullaryMask<VReg RegClass> :
// Nullary for pseudo instructions. They are expanded in
// RISCVExpandPseudoInsts pass.
class VPseudoNullaryPseudoM<string BaseInst> :
- Pseudo<(outs VR:$rd), (ins AVL:$vl, sew_mask:$sew), []>,
- RISCVVPseudo {
+ RISCVVPseudo<(outs VR:$rd), (ins AVL:$vl, sew_mask:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1041,10 +1031,9 @@ class VPseudoUnaryNoMask<DAGOperand RetClass,
DAGOperand OpClass,
string Constraint = "",
bits<2> TargetConstraintType = 1> :
- Pseudo<(outs RetClass:$rd),
+ RISCVVPseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, OpClass:$rs2,
- AVL:$vl, sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo {
+ AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1059,9 +1048,8 @@ class VPseudoUnaryNoMaskNoPolicy<DAGOperand RetClass,
DAGOperand OpClass,
string Constraint = "",
bits<2> TargetConstraintType = 1> :
- Pseudo<(outs RetClass:$rd),
- (ins OpClass:$rs2, AVL:$vl, sew_mask:$sew), []>,
- RISCVVPseudo {
+ RISCVVPseudo<(outs RetClass:$rd),
+ (ins OpClass:$rs2, AVL:$vl, sew_mask:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1075,10 +1063,9 @@ class VPseudoUnaryNoMaskRoundingMode<DAGOperand RetClass,
DAGOperand OpClass,
string Constraint = "",
bits<2> TargetConstraintType = 1> :
- Pseudo<(outs RetClass:$rd),
+ RISCVVPseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, OpClass:$rs2, vec_rm:$rm,
- AVL:$vl, sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo {
+ AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1097,10 +1084,9 @@ class VPseudoUnaryMask<VReg RetClass,
string Constraint = "",
bits<2> TargetConstraintType = 1,
DAGOperand sewop = sew> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
+ RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
- VMaskOp:$vm, AVL:$vl, sewop:$sew, vec_policy:$policy), []>,
- RISCVVPseudo {
+ VMaskOp:$vm, AVL:$vl, sewop:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1117,11 +1103,10 @@ class VPseudoUnaryMaskRoundingMode<VReg RetClass,
VReg OpClass,
string Constraint = "",
bits<2> TargetConstraintType = 1> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
+ RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
VMaskOp:$vm, vec_rm:$rm,
- AVL:$vl, sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo {
+ AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1155,9 +1140,8 @@ class VPseudoUnaryMask_NoExcept<VReg RetClass,
}
class VPseudoUnaryNoMaskGPROut :
- Pseudo<(outs GPR:$rd),
- (ins VR:$rs2, AVL:$vl, sew_mask:$sew), []>,
- RISCVVPseudo {
+ RISCVVPseudo<(outs GPR:$rd),
+ (ins VR:$rs2, AVL:$vl, sew_mask:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1166,9 +1150,8 @@ class VPseudoUnaryNoMaskGPROut :
}
class VPseudoUnaryMaskGPROut :
- Pseudo<(outs GPR:$rd),
- (ins VR:$rs1, VMaskOp:$vm, AVL:$vl, sew_mask:$sew), []>,
- RISCVVPseudo {
+ RISCVVPseudo<(outs GPR:$rd),
+ (ins VR:$rs1, VMaskOp:$vm, AVL:$vl, sew_mask:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1180,10 +1163,9 @@ class VPseudoUnaryMaskGPROut :
// Mask can be V0~V31
class VPseudoUnaryAnyMask<VReg RetClass,
VReg Op1Class> :
- Pseudo<(outs RetClass:$rd),
+ RISCVVPseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, Op1Class:$rs2,
- VR:$vm, AVL:$vl, sew:$sew), []>,
- RISCVVPseudo {
+ VR:$vm, AVL:$vl, sew:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1198,9 +1180,8 @@ class VPseudoBinaryNoMask<VReg RetClass,
string Constraint,
bits<2> TargetConstraintType = 1,
DAGOperand sewop = sew> :
- Pseudo<(outs RetClass:$rd),
- (ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, sewop:$sew), []>,
- RISCVVPseudo {
+ RISCVVPseudo<(outs RetClass:$rd),
+ (ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, sewop:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1215,10 +1196,9 @@ class VPseudoBinaryNoMaskPolicy<VReg RetClass,
DAGOperand Op2Class,
string Constraint,
bits<2> TargetConstraintType = 1> :
- Pseudo<(outs RetClass:$rd),
+ RISCVVPseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, AVL:$vl,
- sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo {
+ sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1235,10 +1215,9 @@ class VPseudoBinaryNoMaskRoundingMode<VReg RetClass,
string Constraint,
bit UsesVXRM_ = 1,
bits<2> TargetConstraintType = 1> :
- Pseudo<(outs RetClass:$rd),
+ RISCVVPseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, vec_rm:$rm,
- AVL:$vl, sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo {
+ AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1258,12 +1237,11 @@ class VPseudoBinaryMaskPolicyRoundingMode<VReg RetClass,
string Constraint,
bit UsesVXRM_,
bits<2> TargetConstraintType = 1> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
+ RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
Op1Class:$rs2, Op2Class:$rs1,
VMaskOp:$vm, vec_rm:$rm, AVL:$vl,
- sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo {
+ sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1286,10 +1264,9 @@ class VPseudoTiedBinaryNoMask<VReg RetClass,
DAGOperand Op2Class,
string Constraint,
bits<2> TargetConstraintType = 1> :
- Pseudo<(outs RetClass:$rd),
+ RISCVVPseudo<(outs RetClass:$rd),
(ins RetClass:$rs2, Op2Class:$rs1, AVL:$vl, sew:$sew,
- vec_policy:$policy), []>,
- RISCVVPseudo {
+ vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1307,12 +1284,11 @@ class VPseudoTiedBinaryNoMaskRoundingMode<VReg RetClass,
DAGOperand Op2Class,
string Constraint,
bits<2> TargetConstraintType = 1> :
- Pseudo<(outs RetClass:$rd),
+ RISCVVPseudo<(outs RetClass:$rd),
(ins RetClass:$rs2, Op2Class:$rs1,
vec_rm:$rm,
AVL:$vl, sew:$sew,
- vec_policy:$policy), []>,
- RISCVVPseudo {
+ vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1331,10 +1307,9 @@ class VPseudoTiedBinaryNoMaskRoundingMode<VReg RetClass,
class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
bit Ordered>:
- Pseudo<(outs),
+ RISCVVPseudo<(outs),
(ins StClass:$rd, GPRMemZeroOffset:$rs1, IdxClass:$rs2, AVL:$vl,
sew:$sew),[]>,
- RISCVVPseudo,
RISCVVSX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 0;
let mayStore = 1;
@@ -1345,10 +1320,9 @@ class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
class VPseudoIStoreMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
bit Ordered>:
- Pseudo<(outs),
+ RISCVVPseudo<(outs),
(ins StClass:$rd, GPRMemZeroOffset:$rs1, IdxClass:$rs2,
VMaskOp:$vm, AVL:$vl, sew:$sew),[]>,
- RISCVVPseudo,
RISCVVSX</*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 0;
let mayStore = 1;
@@ -1363,11 +1337,10 @@ class VPseudoBinaryMaskPolicy<VReg RetClass,
DAGOperand Op2Class,
string Constraint,
bits<2> TargetConstraintType = 1> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
+ RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
Op1Class:$rs2, Op2Class:$rs1,
- VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo {
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1383,11 +1356,10 @@ class VPseudoBinaryMaskPolicy<VReg RetClass,
class VPseudoTernaryMaskPolicy<VReg RetClass,
RegisterClass Op1Class,
DAGOperand Op2Class> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
+ RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
Op1Class:$rs2, Op2Class:$rs1,
- VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo {
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1401,13 +1373,12 @@ class VPseudoTernaryMaskPolicy<VReg RetClass,
class VPseudoTernaryMaskPolicyRoundingMode<VReg RetClass,
RegisterClass Op1Class,
DAGOperand Op2Class> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
+ RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
Op1Class:$rs2, Op2Class:$rs1,
VMaskOp:$vm,
vec_rm:$rm,
- AVL:$vl, sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo {
+ AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1427,11 +1398,10 @@ class VPseudoBinaryMOutMask<VReg RetClass,
DAGOperand Op2Class,
string Constraint,
bits<2> TargetConstraintType = 1> :
- Pseudo<(outs RetClass:$rd),
+ RISCVVPseudo<(outs RetClass:$rd),
(ins RetClass:$passthru,
Op1Class:$rs2, Op2Class:$rs1,
- VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo {
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1451,11 +1421,10 @@ class VPseudoTiedBinaryMask<VReg RetClass,
DAGOperand Op2Class,
string Constraint,
bits<2> TargetConstraintType = 1> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
+ RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
Op2Class:$rs1,
- VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo {
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1473,13 +1442,12 @@ class VPseudoTiedBinaryMaskRoundingMode<VReg RetClass,
DAGOperand Op2Class,
string Constraint,
bits<2> TargetConstraintType = 1> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
+ RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
Op2Class:$rs1,
VMaskOp:$vm,
vec_rm:$rm,
- AVL:$vl, sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo {
+ AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1503,13 +1471,12 @@ class VPseudoBinaryCarry<VReg RetClass,
bit CarryIn,
string Constraint,
bits<2> TargetConstraintType = 1> :
- Pseudo<(outs RetClass:$rd),
+ RISCVVPseudo<(outs RetClass:$rd),
!if(CarryIn,
(ins Op1Class:$rs2, Op2Class:$rs1,
VMV0:$carry, AVL:$vl, sew:$sew),
(ins Op1Class:$rs2, Op2Class:$rs1,
- AVL:$vl, sew:$sew)), []>,
- RISCVVPseudo {
+ AVL:$vl, sew:$sew)), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1525,10 +1492,9 @@ class VPseudoTiedBinaryCarryIn<VReg RetClass,
DAGOperand Op2Class,
LMULInfo MInfo,
bits<2> TargetConstraintType = 1> :
- Pseudo<(outs RetClass:$rd),
+ RISCVVPseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1,
- VMV0:$carry, AVL:$vl, sew:$sew), []>,
- RISCVVPseudo {
+ VMV0:$carry, AVL:$vl, sew:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1544,10 +1510,9 @@ class VPseudoTernaryNoMask<VReg RetClass,
RegisterClass Op1Class,
DAGOperand Op2Class,
string Constraint> :
- Pseudo<(outs RetClass:$rd),
+ RISCVVPseudo<(outs RetClass:$rd),
(ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
- AVL:$vl, sew:$sew), []>,
- RISCVVPseudo {
+ AVL:$vl, sew:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1561,10 +1526,9 @@ class VPseudoTernaryNoMaskWithPolicy<VReg RetClass,
DAGOperand Op2Class,
string Constraint = "",
bits<2> TargetConstraintType = 1> :
- Pseudo<(outs RetClass:$rd),
+ RISCVVPseudo<(outs RetClass:$rd),
(ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
- AVL:$vl, sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo {
+ AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1580,10 +1544,9 @@ class VPseudoTernaryNoMaskWithPolicyRoundingMode<VReg RetClass,
DAGOperand Op2Class,
string Constraint = "",
bits<2> TargetConstraintType = 1> :
- Pseudo<(outs RetClass:$rd),
+ RISCVVPseudo<(outs RetClass:$rd),
(ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
- vec_rm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo {
+ vec_rm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1600,10 +1563,9 @@ class VPseudoTernaryNoMaskWithPolicyRoundingMode<VReg RetClass,
class VPseudoUSSegLoadNoMask<VReg RetClass,
int EEW,
bits<4> NF> :
- Pseudo<(outs RetClass:$rd),
+ RISCVVPseudo<(outs RetClass:$rd),
(ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$vl,
sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo,
RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
@@ -1617,10 +1579,9 @@ class VPseudoUSSegLoadNoMask<VReg RetClass,
class VPseudoUSSegLoadMask<VReg RetClass,
int EEW,
bits<4> NF> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
+ RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMemZeroOffset:$rs1,
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo,
RISCVVLSEG<NF, /*Masked*/1, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
@@ -1636,10 +1597,9 @@ class VPseudoUSSegLoadMask<VReg RetClass,
class VPseudoUSSegLoadFFNoMask<VReg RetClass,
int EEW,
bits<4> NF> :
- Pseudo<(outs RetClass:$rd, GPR:$vl),
+ RISCVVPseudo<(outs RetClass:$rd, GPR:$vl),
(ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$avl,
sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo,
RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
@@ -1653,10 +1613,9 @@ class VPseudoUSSegLoadFFNoMask<VReg RetClass,
class VPseudoUSSegLoadFFMask<VReg RetClass,
int EEW,
bits<4> NF> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl),
+ RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl),
(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMemZeroOffset:$rs1,
VMaskOp:$vm, AVL:$avl, sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo,
RISCVVLSEG<NF, /*Masked*/1, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
@@ -1672,10 +1631,9 @@ class VPseudoUSSegLoadFFMask<VReg RetClass,
class VPseudoSSegLoadNoMask<VReg RetClass,
int EEW,
bits<4> NF> :
- Pseudo<(outs RetClass:$rd),
+ RISCVVPseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, GPRMemZeroOffset:$rs1, GPR:$offset, AVL:$vl,
sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo,
RISCVVLSEG<NF, /*Masked*/0, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
@@ -1689,11 +1647,10 @@ class VPseudoSSegLoadNoMask<VReg RetClass,
class VPseudoSSegLoadMask<VReg RetClass,
int EEW,
bits<4> NF> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
+ RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMemZeroOffset:$rs1,
GPR:$offset, VMaskOp:$vm, AVL:$vl, sew:$sew,
vec_policy:$policy), []>,
- RISCVVPseudo,
RISCVVLSEG<NF, /*Masked*/1, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
@@ -1712,10 +1669,9 @@ class VPseudoISegLoadNoMask<VReg RetClass,
bits<3> LMUL,
bits<4> NF,
bit Ordered> :
- Pseudo<(outs RetClass:$rd),
+ RISCVVPseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, GPRMemZeroOffset:$rs1, IdxClass:$offset, AVL:$vl,
sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo,
RISCVVLXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 1;
let mayStore = 0;
@@ -1734,11 +1690,10 @@ class VPseudoISegLoadMask<VReg RetClass,
bits<3> LMUL,
bits<4> NF,
bit Ordered> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
+ RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMemZeroOffset:$rs1,
IdxClass:$offset, VMaskOp:$vm, AVL:$vl, sew:$sew,
vec_policy:$policy), []>,
- RISCVVPseudo,
RISCVVLXSEG<NF, /*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 1;
let mayStore = 0;
@@ -1756,9 +1711,8 @@ class VPseudoISegLoadMask<VReg RetClass,
class VPseudoUSSegStoreNoMask<VReg ValClass,
int EEW,
bits<4> NF> :
- Pseudo<(outs),
+ RISCVVPseudo<(outs),
(ins ValClass:$rd, GPRMemZeroOffset:$rs1, AVL:$vl, sew:$sew), []>,
- RISCVVPseudo,
RISCVVSSEG<NF, /*Masked*/0, /*Strided*/0, !logtwo(EEW), VLMul> {
let mayLoad = 0;
let mayStore = 1;
@@ -1770,10 +1724,9 @@ class VPseudoUSSegStoreNoMask<VReg ValClass,
class VPseudoUSSegStoreMask<VReg ValClass,
int EEW,
bits<4> NF> :
- Pseudo<(outs),
+ RISCVVPseudo<(outs),
(ins ValClass:$rd, GPRMemZeroOffset:$rs1,
VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
- RISCVVPseudo,
RISCVVSSEG<NF, /*Masked*/1, /*Strided*/0, !logtwo(EEW), VLMul> {
let mayLoad = 0;
let mayStore = 1;
@@ -1786,10 +1739,9 @@ class VPseudoUSSegStoreMask<VReg ValClass,
class VPseudoSSegStoreNoMask<VReg ValClass,
int EEW,
bits<4> NF> :
- Pseudo<(outs),
+ RISCVVPseudo<(outs),
(ins ValClass:$rd, GPRMemZeroOffset:$rs1, GPR:$offset,
AVL:$vl, sew:$sew), []>,
- RISCVVPseudo,
RISCVVSSEG<NF, /*Masked*/0, /*Strided*/1, !logtwo(EEW), VLMul> {
let mayLoad = 0;
let mayStore = 1;
@@ -1801,10 +1753,9 @@ class VPseudoSSegStoreNoMask<VReg ValClass,
class VPseudoSSegStoreMask<VReg ValClass,
int EEW,
bits<4> NF> :
- Pseudo<(outs),
+ RISCVVPseudo<(outs),
(ins ValClass:$rd, GPRMemZeroOffset:$rs1, GPR: $offset,
VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
- RISCVVPseudo,
RISCVVSSEG<NF, /*Masked*/1, /*Strided*/1, !logtwo(EEW), VLMul> {
let mayLoad = 0;
let mayStore = 1;
@@ -1820,10 +1771,9 @@ class VPseudoISegStoreNoMask<VReg ValClass,
bits<3> LMUL,
bits<4> NF,
bit Ordered> :
- Pseudo<(outs),
+ RISCVVPseudo<(outs),
(ins ValClass:$rd, GPRMemZeroOffset:$rs1, IdxClass: $index,
AVL:$vl, sew:$sew), []>,
- RISCVVPseudo,
RISCVVSXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 0;
let mayStore = 1;
@@ -1838,10 +1788,9 @@ class VPseudoISegStoreMask<VReg ValClass,
bits<3> LMUL,
bits<4> NF,
bit Ordered> :
- Pseudo<(outs),
+ RISCVVPseudo<(outs),
(ins ValClass:$rd, GPRMemZeroOffset:$rs1, IdxClass: $index,
VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
- RISCVVPseudo,
RISCVVSXSEG<NF, /*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 0;
let mayStore = 1;
@@ -6745,16 +6694,14 @@ let Predicates = [HasVInstructions] in {
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
let HasSEWOp = 1, BaseInstr = VMV_X_S in
def PseudoVMV_X_S:
- Pseudo<(outs GPR:$rd), (ins VR:$rs2, sew:$sew), []>,
- Sched<[WriteVMovXS, ReadVMovXS]>,
- RISCVVPseudo;
+ RISCVVPseudo<(outs GPR:$rd), (ins VR:$rs2, sew:$sew), []>,
+ Sched<[WriteVMovXS, ReadVMovXS]>;
let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X, isReMaterializable = 1,
Constraints = "$rd = $passthru" in
- def PseudoVMV_S_X: Pseudo<(outs VR:$rd),
+ def PseudoVMV_S_X: RISCVVPseudo<(outs VR:$rd),
(ins VR:$passthru, GPR:$rs1, AVL:$vl, sew:$sew),
[]>,
- Sched<[WriteVMovSX, ReadVMovSX_V, ReadVMovSX_X]>,
- RISCVVPseudo;
+ Sched<[WriteVMovSX, ReadVMovSX_V, ReadVMovSX_X]>;
}
} // Predicates = [HasVInstructions]
@@ -6767,18 +6714,16 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
foreach f = FPList in {
let HasSEWOp = 1, BaseInstr = VFMV_F_S in
def "PseudoVFMV_" # f.FX # "_S" :
- Pseudo<(outs f.fprclass:$rd),
+ RISCVVPseudo<(outs f.fprclass:$rd),
(ins VR:$rs2, sew:$sew), []>,
- Sched<[WriteVMovFS, ReadVMovFS]>,
- RISCVVPseudo;
+ Sched<[WriteVMovFS, ReadVMovFS]>;
let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F, isReMaterializable = 1,
Constraints = "$rd = $passthru" in
def "PseudoVFMV_S_" # f.FX :
- Pseudo<(outs VR:$rd),
+ RISCVVPseudo<(outs VR:$rd),
(ins VR:$passthru, f.fprclass:$rs1, AVL:$vl, sew:$sew),
[]>,
- Sched<[WriteVMovSF, ReadVMovSF_V, ReadVMovSF_F]>,
- RISCVVPseudo;
+ Sched<[WriteVMovSF, ReadVMovSF_V, ReadVMovSF_F]>;
}
}
} // Predicates = [HasVInstructionsAnyF]
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
index 5220815336441..786183421feed 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
@@ -448,11 +448,10 @@ class NDSRVInstVLN<bits<5> funct5, string opcodestr>
}
class VPseudoVLN8NoMask<VReg RetClass, bit U> :
- Pseudo<(outs RetClass:$rd),
+ RISCVVPseudo<(outs RetClass:$rd),
(ins RetClass:$dest,
GPRMemZeroOffset:$rs1,
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo,
RISCVNDSVLN</*Masked*/0, /*Unsigned*/U, !logtwo(8), VLMul> {
let mayLoad = 1;
let mayStore = 0;
@@ -464,11 +463,10 @@ class VPseudoVLN8NoMask<VReg RetClass, bit U> :
}
class VPseudoVLN8Mask<VReg RetClass, bit U> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
+ RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
GPRMemZeroOffset:$rs1,
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo,
RISCVNDSVLN</*Masked*/1, /*Unsigned*/U, !logtwo(8), VLMul> {
let mayLoad = 1;
let mayStore = 0;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
index 3912eb0d16c59..5395f3b3d52be 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
@@ -154,18 +154,16 @@ foreach m = MxList in {
let VLMul = m.value in {
let BaseInstr = RI_VEXTRACT in
def PseudoRI_VEXTRACT_ # mx :
- Pseudo<(outs GPR:$rd), (ins m.vrclass:$rs2, uimm5:$idx, ixlenimm:$sew),
- []>,
- RISCVVPseudo;
+ RISCVVPseudo<(outs GPR:$rd), (ins m.vrclass:$rs2, uimm5:$idx, ixlenimm:$sew),
+ []>;
let HasVLOp = 1, BaseInstr = RI_VINSERT, HasVecPolicyOp = 1,
Constraints = "$rd = $rs1" in
def PseudoRI_VINSERT_ # mx :
- Pseudo<(outs m.vrclass:$rd),
+ RISCVVPseudo<(outs m.vrclass:$rd),
(ins m.vrclass:$rs1, GPR:$rs2, uimm5:$idx, AVL:$vl,
ixlenimm:$sew, ixlenimm:$policy),
- []>,
- RISCVVPseudo;
+ []>;
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
index 17fb75eb851c4..87e0b1b93bb0f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
@@ -243,10 +243,9 @@ let Predicates = [HasVendorXSfvfnrclipxfqf], DecoderNamespace = "XSfvector",
}
class VPseudoVC_X<Operand OpClass, DAGOperand RS1Class> :
- Pseudo<(outs),
+ RISCVVPseudo<(outs),
(ins OpClass:$op1, payload5:$rs2, payload5:$rd, RS1Class:$r1,
- AVL:$vl, sew:$sew), []>,
- RISCVVPseudo {
+ AVL:$vl, sew:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let HasVLOp = 1;
@@ -255,10 +254,9 @@ class VPseudoVC_X<Operand OpClass, DAGOperand RS1Class> :
}
class VPseudoVC_XV<Operand OpClass, VReg RS2Class, DAGOperand RS1Class> :
- Pseudo<(outs),
+ RISCVVPseudo<(outs),
(ins OpClass:$op1, payload5:$rd, RS2Class:$rs2, RS1Class:$r1,
- AVL:$vl, sew:$sew), []>,
- RISCVVPseudo {
+ AVL:$vl, sew:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let HasVLOp = 1;
@@ -268,10 +266,9 @@ class VPseudoVC_XV<Operand OpClass, VReg RS2Class, DAGOperand RS1Class> :
class VPseudoVC_XVV<Operand OpClass, VReg RDClass, VReg RS2Class,
DAGOperand RS1Class> :
- Pseudo<(outs),
+ RISCVVPseudo<(outs),
(ins OpClass:$op1, RDClass:$rd, RS2Class:$rs2, RS1Class:$r1,
- AVL:$vl, sew:$sew), []>,
- RISCVVPseudo {
+ AVL:$vl, sew:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let HasVLOp = 1;
@@ -280,10 +277,9 @@ class VPseudoVC_XVV<Operand OpClass, VReg RDClass, VReg RS2Class,
}
class VPseudoVC_V_X<Operand OpClass, VReg RDClass, DAGOperand RS1Class> :
- Pseudo<(outs RDClass:$rd),
+ RISCVVPseudo<(outs RDClass:$rd),
(ins OpClass:$op1, payload5:$rs2, RS1Class:$r1,
- AVL:$vl, sew:$sew), []>,
- RISCVVPseudo {
+ AVL:$vl, sew:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let HasVLOp = 1;
@@ -293,10 +289,9 @@ class VPseudoVC_V_X<Operand OpClass, VReg RDClass, DAGOperand RS1Class> :
class VPseudoVC_V_XV<Operand OpClass, VReg RDClass, VReg RS2Class,
DAGOperand RS1Class> :
- Pseudo<(outs RDClass:$rd),
+ RISCVVPseudo<(outs RDClass:$rd),
(ins OpClass:$op1, RS2Class:$rs2, RS1Class:$r1,
- AVL:$vl, sew:$sew), []>,
- RISCVVPseudo {
+ AVL:$vl, sew:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let HasVLOp = 1;
@@ -306,10 +301,9 @@ class VPseudoVC_V_XV<Operand OpClass, VReg RDClass, VReg RS2Class,
class VPseudoVC_V_XVV<Operand OpClass, VReg RDClass, VReg RS2Class,
DAGOperand RS1Class> :
- Pseudo<(outs RDClass:$rd),
+ RISCVVPseudo<(outs RDClass:$rd),
(ins OpClass:$op1, RDClass:$rs3, RS2Class:$rs2, RS1Class:$r1,
- AVL:$vl, sew:$sew), []>,
- RISCVVPseudo {
+ AVL:$vl, sew:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let HasVLOp = 1;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index 4147c97a7a23a..a250ac8d3e260 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -230,9 +230,8 @@ class ZvkMxSet<string vd_lmul> {
}
class VPseudoBinaryNoMask_Zvk<DAGOperand RetClass, VReg OpClass> :
- Pseudo<(outs RetClass:$rd_wb),
- (ins RetClass:$rd, OpClass:$rs2, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo {
+ RISCVVPseudo<(outs RetClass:$rd_wb),
+ (ins RetClass:$rd, OpClass:$rs2, AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -246,10 +245,9 @@ class VPseudoBinaryNoMask_Zvk<DAGOperand RetClass, VReg OpClass> :
class VPseudoTernaryNoMask_Zvk<VReg RetClass,
VReg Op1Class,
DAGOperand Op2Class> :
- Pseudo<(outs RetClass:$rd_wb),
+ RISCVVPseudo<(outs RetClass:$rd_wb),
(ins RetClass:$rd, Op1Class:$rs2, Op2Class:$rs1,
- AVL:$vl, sew:$sew, vec_policy:$policy), []>,
- RISCVVPseudo {
+ AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index 15bd3466373a7..ee63e19350a9f 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -33,7 +33,6 @@ namespace {
class RISCVVLOptimizer : public MachineFunctionPass {
const MachineRegisterInfo *MRI;
const MachineDominatorTree *MDT;
- const TargetInstrInfo *TII;
public:
static char ID;
@@ -1292,8 +1291,7 @@ bool RISCVVLOptimizer::isCandidate(const MachineInstr &MI) const {
return false;
}
- assert(!RISCVII::elementsDependOnVL(
- TII->get(RISCV::getRVVMCOpcode(MI.getOpcode())).TSFlags) &&
+ assert(!RISCVII::elementsDependOnVL(MI.getDesc().TSFlags) &&
"Instruction shouldn't be supported if elements depend on VL");
assert(MI.getOperand(0).isReg() &&
@@ -1497,8 +1495,6 @@ bool RISCVVLOptimizer::runOnMachineFunction(MachineFunction &MF) {
if (!ST.hasVInstructions())
return false;
- TII = ST.getInstrInfo();
-
// For each instruction that defines a vector, compute what VL its
// downstream users demand.
for (MachineBasicBlock *MBB : post_order(&MF)) {
diff --git a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
index 84ef53985484f..b249795dfe52d 100644
--- a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
@@ -91,8 +91,7 @@ bool RISCVVectorPeephole::hasSameEEW(const MachineInstr &User,
User.getOperand(RISCVII::getSEWOpNum(User.getDesc())).getImm();
unsigned SrcLog2SEW =
Src.getOperand(RISCVII::getSEWOpNum(Src.getDesc())).getImm();
- unsigned SrcLog2EEW = RISCV::getDestLog2EEW(
- TII->get(RISCV::getRVVMCOpcode(Src.getOpcode())), SrcLog2SEW);
+ unsigned SrcLog2EEW = RISCV::getDestLog2EEW(Src.getDesc(), SrcLog2SEW);
return SrcLog2EEW == UserLog2SEW;
}
@@ -170,8 +169,8 @@ bool RISCVVectorPeephole::tryToReduceVL(MachineInstr &MI) const {
if (!hasSameEEW(MI, *Src))
continue;
- bool ElementsDependOnVL = RISCVII::elementsDependOnVL(
- TII->get(RISCV::getRVVMCOpcode(Src->getOpcode())).TSFlags);
+ bool ElementsDependOnVL =
+ RISCVII::elementsDependOnVL(Src->getDesc().TSFlags);
if (ElementsDependOnVL || Src->mayRaiseFPException())
continue;
@@ -760,11 +759,11 @@ bool RISCVVectorPeephole::foldVMergeToMask(MachineInstr &MI) const {
else
return false;
- unsigned RVVTSFlags =
- TII->get(RISCV::getRVVMCOpcode(True.getOpcode())).TSFlags;
- if (RISCVII::elementsDependOnVL(RVVTSFlags) && !TrueVL.isIdenticalTo(MinVL))
+ if (RISCVII::elementsDependOnVL(True.getDesc().TSFlags) &&
+ !TrueVL.isIdenticalTo(MinVL))
return false;
- if (RISCVII::elementsDependOnMask(RVVTSFlags) && !isAllOnesMask(Mask))
+ if (RISCVII::elementsDependOnMask(True.getDesc().TSFlags) &&
+ !isAllOnesMask(Mask))
return false;
// Use a tumu policy, relaxing it to tail agnostic provided that the passthru
>From 7321018798c0e51225850381ac87e2795d094f27 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Tue, 22 Jul 2025 00:37:14 +0800
Subject: [PATCH 2/3] Indent tablgen properly
---
.../Target/RISCV/RISCVInstrInfoVPseudos.td | 269 +++++++++---------
llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td | 13 +-
llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td | 11 +-
llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td | 24 +-
4 files changed, 166 insertions(+), 151 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 7d3e799bb205f..1b6db9b664771 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -791,8 +791,8 @@ class VPseudoUSLoadNoMask<VReg RetClass,
int EEW,
DAGOperand sewop = sew> :
RISCVVPseudo<(outs RetClass:$rd),
- (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$vl, sewop:$sew,
- vec_policy:$policy), []>,
+ (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$vl,
+ sewop:$sew, vec_policy:$policy), []>,
RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
@@ -806,9 +806,9 @@ class VPseudoUSLoadNoMask<VReg RetClass,
class VPseudoUSLoadMask<VReg RetClass,
int EEW> :
RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$passthru,
- GPRMemZeroOffset:$rs1,
- VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
+ (ins GetVRegNoV0<RetClass>.R:$passthru,
+ GPRMemZeroOffset:$rs1, VMaskOp:$vm, AVL:$vl, sew:$sew,
+ vec_policy:$policy), []>,
RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
@@ -824,8 +824,8 @@ class VPseudoUSLoadMask<VReg RetClass,
class VPseudoUSLoadFFNoMask<VReg RetClass,
int EEW> :
RISCVVPseudo<(outs RetClass:$rd, GPR:$vl),
- (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$avl,
- sew:$sew, vec_policy:$policy), []>,
+ (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$avl,
+ sew:$sew, vec_policy:$policy), []>,
RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
@@ -839,9 +839,9 @@ class VPseudoUSLoadFFNoMask<VReg RetClass,
class VPseudoUSLoadFFMask<VReg RetClass,
int EEW> :
RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl),
- (ins GetVRegNoV0<RetClass>.R:$passthru,
- GPRMemZeroOffset:$rs1,
- VMaskOp:$vm, AVL:$avl, sew:$sew, vec_policy:$policy), []>,
+ (ins GetVRegNoV0<RetClass>.R:$passthru,
+ GPRMemZeroOffset:$rs1, VMaskOp:$vm, AVL:$avl, sew:$sew,
+ vec_policy:$policy), []>,
RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
@@ -857,8 +857,8 @@ class VPseudoUSLoadFFMask<VReg RetClass,
class VPseudoSLoadNoMask<VReg RetClass,
int EEW> :
RISCVVPseudo<(outs RetClass:$rd),
- (ins RetClass:$dest, GPRMemZeroOffset:$rs1, GPR:$rs2, AVL:$vl,
- sew:$sew, vec_policy:$policy), []>,
+ (ins RetClass:$dest, GPRMemZeroOffset:$rs1, GPR:$rs2,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVLE</*Masked*/0, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
@@ -872,9 +872,9 @@ class VPseudoSLoadNoMask<VReg RetClass,
class VPseudoSLoadMask<VReg RetClass,
int EEW> :
RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$passthru,
- GPRMemZeroOffset:$rs1, GPR:$rs2,
- VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
+ (ins GetVRegNoV0<RetClass>.R:$passthru,
+ GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm, AVL:$vl,
+ sew:$sew, vec_policy:$policy), []>,
RISCVVLE</*Masked*/1, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
@@ -895,8 +895,8 @@ class VPseudoILoadNoMask<VReg RetClass,
bit EarlyClobber,
bits<2> TargetConstraintType = 1> :
RISCVVPseudo<(outs RetClass:$rd),
- (ins RetClass:$dest, GPRMemZeroOffset:$rs1, IdxClass:$rs2, AVL:$vl,
- sew:$sew, vec_policy:$policy), []>,
+ (ins RetClass:$dest, GPRMemZeroOffset:$rs1, IdxClass:$rs2,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVLX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 1;
let mayStore = 0;
@@ -916,9 +916,9 @@ class VPseudoILoadMask<VReg RetClass,
bit EarlyClobber,
bits<2> TargetConstraintType = 1> :
RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$passthru,
- GPRMemZeroOffset:$rs1, IdxClass:$rs2,
- VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
+ (ins GetVRegNoV0<RetClass>.R:$passthru,
+ GPRMemZeroOffset:$rs1, IdxClass:$rs2, VMaskOp:$vm,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVLX</*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 1;
let mayStore = 0;
@@ -936,7 +936,8 @@ class VPseudoUSStoreNoMask<VReg StClass,
int EEW,
DAGOperand sewop = sew> :
RISCVVPseudo<(outs),
- (ins StClass:$rd, GPRMemZeroOffset:$rs1, AVL:$vl, sewop:$sew), []>,
+ (ins StClass:$rd, GPRMemZeroOffset:$rs1, AVL:$vl,
+ sewop:$sew), []>,
RISCVVSE</*Masked*/0, /*Strided*/0, !logtwo(EEW), VLMul> {
let mayLoad = 0;
let mayStore = 1;
@@ -948,8 +949,8 @@ class VPseudoUSStoreNoMask<VReg StClass,
class VPseudoUSStoreMask<VReg StClass,
int EEW> :
RISCVVPseudo<(outs),
- (ins StClass:$rd, GPRMemZeroOffset:$rs1,
- VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
+ (ins StClass:$rd, GPRMemZeroOffset:$rs1,
+ VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
RISCVVSE</*Masked*/1, /*Strided*/0, !logtwo(EEW), VLMul> {
let mayLoad = 0;
let mayStore = 1;
@@ -962,8 +963,8 @@ class VPseudoUSStoreMask<VReg StClass,
class VPseudoSStoreNoMask<VReg StClass,
int EEW> :
RISCVVPseudo<(outs),
- (ins StClass:$rd, GPRMemZeroOffset:$rs1, GPR:$rs2,
- AVL:$vl, sew:$sew), []>,
+ (ins StClass:$rd, GPRMemZeroOffset:$rs1, GPR:$rs2,
+ AVL:$vl, sew:$sew), []>,
RISCVVSE</*Masked*/0, /*Strided*/1, !logtwo(EEW), VLMul> {
let mayLoad = 0;
let mayStore = 1;
@@ -975,8 +976,8 @@ class VPseudoSStoreNoMask<VReg StClass,
class VPseudoSStoreMask<VReg StClass,
int EEW> :
RISCVVPseudo<(outs),
- (ins StClass:$rd, GPRMemZeroOffset:$rs1, GPR:$rs2,
- VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
+ (ins StClass:$rd, GPRMemZeroOffset:$rs1, GPR:$rs2,
+ VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
RISCVVSE</*Masked*/1, /*Strided*/1, !logtwo(EEW), VLMul> {
let mayLoad = 0;
let mayStore = 1;
@@ -988,8 +989,8 @@ class VPseudoSStoreMask<VReg StClass,
class VPseudoNullaryNoMask<VReg RegClass> :
RISCVVPseudo<(outs RegClass:$rd),
- (ins RegClass:$passthru,
- AVL:$vl, sew:$sew, vec_policy:$policy), []> {
+ (ins RegClass:$passthru,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1001,8 +1002,9 @@ class VPseudoNullaryNoMask<VReg RegClass> :
class VPseudoNullaryMask<VReg RegClass> :
RISCVVPseudo<(outs GetVRegNoV0<RegClass>.R:$rd),
- (ins GetVRegNoV0<RegClass>.R:$passthru,
- VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []> {
+ (ins GetVRegNoV0<RegClass>.R:$passthru,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy),
+ []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1032,8 +1034,8 @@ class VPseudoUnaryNoMask<DAGOperand RetClass,
string Constraint = "",
bits<2> TargetConstraintType = 1> :
RISCVVPseudo<(outs RetClass:$rd),
- (ins RetClass:$passthru, OpClass:$rs2,
- AVL:$vl, sew:$sew, vec_policy:$policy), []> {
+ (ins RetClass:$passthru, OpClass:$rs2,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1049,7 +1051,7 @@ class VPseudoUnaryNoMaskNoPolicy<DAGOperand RetClass,
string Constraint = "",
bits<2> TargetConstraintType = 1> :
RISCVVPseudo<(outs RetClass:$rd),
- (ins OpClass:$rs2, AVL:$vl, sew_mask:$sew), []> {
+ (ins OpClass:$rs2, AVL:$vl, sew_mask:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1064,8 +1066,8 @@ class VPseudoUnaryNoMaskRoundingMode<DAGOperand RetClass,
string Constraint = "",
bits<2> TargetConstraintType = 1> :
RISCVVPseudo<(outs RetClass:$rd),
- (ins RetClass:$passthru, OpClass:$rs2, vec_rm:$rm,
- AVL:$vl, sew:$sew, vec_policy:$policy), []> {
+ (ins RetClass:$passthru, OpClass:$rs2, vec_rm:$rm,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1085,8 +1087,8 @@ class VPseudoUnaryMask<VReg RetClass,
bits<2> TargetConstraintType = 1,
DAGOperand sewop = sew> :
RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
- VMaskOp:$vm, AVL:$vl, sewop:$sew, vec_policy:$policy), []> {
+ (ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
+ VMaskOp:$vm, AVL:$vl, sewop:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1104,9 +1106,9 @@ class VPseudoUnaryMaskRoundingMode<VReg RetClass,
string Constraint = "",
bits<2> TargetConstraintType = 1> :
RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
- VMaskOp:$vm, vec_rm:$rm,
- AVL:$vl, sew:$sew, vec_policy:$policy), []> {
+ (ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
+ VMaskOp:$vm, vec_rm:$rm,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1141,7 +1143,7 @@ class VPseudoUnaryMask_NoExcept<VReg RetClass,
class VPseudoUnaryNoMaskGPROut :
RISCVVPseudo<(outs GPR:$rd),
- (ins VR:$rs2, AVL:$vl, sew_mask:$sew), []> {
+ (ins VR:$rs2, AVL:$vl, sew_mask:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1151,7 +1153,7 @@ class VPseudoUnaryNoMaskGPROut :
class VPseudoUnaryMaskGPROut :
RISCVVPseudo<(outs GPR:$rd),
- (ins VR:$rs1, VMaskOp:$vm, AVL:$vl, sew_mask:$sew), []> {
+ (ins VR:$rs1, VMaskOp:$vm, AVL:$vl, sew_mask:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1164,8 +1166,8 @@ class VPseudoUnaryMaskGPROut :
class VPseudoUnaryAnyMask<VReg RetClass,
VReg Op1Class> :
RISCVVPseudo<(outs RetClass:$rd),
- (ins RetClass:$passthru, Op1Class:$rs2,
- VR:$vm, AVL:$vl, sew:$sew), []> {
+ (ins RetClass:$passthru, Op1Class:$rs2,
+ VR:$vm, AVL:$vl, sew:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1181,7 +1183,8 @@ class VPseudoBinaryNoMask<VReg RetClass,
bits<2> TargetConstraintType = 1,
DAGOperand sewop = sew> :
RISCVVPseudo<(outs RetClass:$rd),
- (ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, sewop:$sew), []> {
+ (ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, sewop:$sew),
+ []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1197,8 +1200,8 @@ class VPseudoBinaryNoMaskPolicy<VReg RetClass,
string Constraint,
bits<2> TargetConstraintType = 1> :
RISCVVPseudo<(outs RetClass:$rd),
- (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, AVL:$vl,
- sew:$sew, vec_policy:$policy), []> {
+ (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1216,8 +1219,9 @@ class VPseudoBinaryNoMaskRoundingMode<VReg RetClass,
bit UsesVXRM_ = 1,
bits<2> TargetConstraintType = 1> :
RISCVVPseudo<(outs RetClass:$rd),
- (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, vec_rm:$rm,
- AVL:$vl, sew:$sew, vec_policy:$policy), []> {
+ (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1,
+ vec_rm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy),
+ []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1238,10 +1242,10 @@ class VPseudoBinaryMaskPolicyRoundingMode<VReg RetClass,
bit UsesVXRM_,
bits<2> TargetConstraintType = 1> :
RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$passthru,
- Op1Class:$rs2, Op2Class:$rs1,
- VMaskOp:$vm, vec_rm:$rm, AVL:$vl,
- sew:$sew, vec_policy:$policy), []> {
+ (ins GetVRegNoV0<RetClass>.R:$passthru,
+ Op1Class:$rs2, Op2Class:$rs1,
+ VMaskOp:$vm, vec_rm:$rm, AVL:$vl,
+ sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1265,8 +1269,8 @@ class VPseudoTiedBinaryNoMask<VReg RetClass,
string Constraint,
bits<2> TargetConstraintType = 1> :
RISCVVPseudo<(outs RetClass:$rd),
- (ins RetClass:$rs2, Op2Class:$rs1, AVL:$vl, sew:$sew,
- vec_policy:$policy), []> {
+ (ins RetClass:$rs2, Op2Class:$rs1, AVL:$vl, sew:$sew,
+ vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1285,10 +1289,10 @@ class VPseudoTiedBinaryNoMaskRoundingMode<VReg RetClass,
string Constraint,
bits<2> TargetConstraintType = 1> :
RISCVVPseudo<(outs RetClass:$rd),
- (ins RetClass:$rs2, Op2Class:$rs1,
- vec_rm:$rm,
- AVL:$vl, sew:$sew,
- vec_policy:$policy), []> {
+ (ins RetClass:$rs2, Op2Class:$rs1,
+ vec_rm:$rm,
+ AVL:$vl, sew:$sew,
+ vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1308,8 +1312,8 @@ class VPseudoTiedBinaryNoMaskRoundingMode<VReg RetClass,
class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
bit Ordered>:
RISCVVPseudo<(outs),
- (ins StClass:$rd, GPRMemZeroOffset:$rs1, IdxClass:$rs2, AVL:$vl,
- sew:$sew),[]>,
+ (ins StClass:$rd, GPRMemZeroOffset:$rs1, IdxClass:$rs2,
+ AVL:$vl, sew:$sew),[]>,
RISCVVSX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 0;
let mayStore = 1;
@@ -1321,8 +1325,8 @@ class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
class VPseudoIStoreMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
bit Ordered>:
RISCVVPseudo<(outs),
- (ins StClass:$rd, GPRMemZeroOffset:$rs1, IdxClass:$rs2,
- VMaskOp:$vm, AVL:$vl, sew:$sew),[]>,
+ (ins StClass:$rd, GPRMemZeroOffset:$rs1, IdxClass:$rs2,
+ VMaskOp:$vm, AVL:$vl, sew:$sew),[]>,
RISCVVSX</*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 0;
let mayStore = 1;
@@ -1338,9 +1342,10 @@ class VPseudoBinaryMaskPolicy<VReg RetClass,
string Constraint,
bits<2> TargetConstraintType = 1> :
RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$passthru,
- Op1Class:$rs2, Op2Class:$rs1,
- VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []> {
+ (ins GetVRegNoV0<RetClass>.R:$passthru,
+ Op1Class:$rs2, Op2Class:$rs1,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy),
+ []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1357,9 +1362,10 @@ class VPseudoTernaryMaskPolicy<VReg RetClass,
RegisterClass Op1Class,
DAGOperand Op2Class> :
RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$passthru,
- Op1Class:$rs2, Op2Class:$rs1,
- VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []> {
+ (ins GetVRegNoV0<RetClass>.R:$passthru,
+ Op1Class:$rs2, Op2Class:$rs1,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy),
+ []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1374,11 +1380,11 @@ class VPseudoTernaryMaskPolicyRoundingMode<VReg RetClass,
RegisterClass Op1Class,
DAGOperand Op2Class> :
RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$passthru,
- Op1Class:$rs2, Op2Class:$rs1,
- VMaskOp:$vm,
- vec_rm:$rm,
- AVL:$vl, sew:$sew, vec_policy:$policy), []> {
+ (ins GetVRegNoV0<RetClass>.R:$passthru,
+ Op1Class:$rs2, Op2Class:$rs1,
+ VMaskOp:$vm,
+ vec_rm:$rm,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1399,9 +1405,10 @@ class VPseudoBinaryMOutMask<VReg RetClass,
string Constraint,
bits<2> TargetConstraintType = 1> :
RISCVVPseudo<(outs RetClass:$rd),
- (ins RetClass:$passthru,
- Op1Class:$rs2, Op2Class:$rs1,
- VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []> {
+ (ins RetClass:$passthru,
+ Op1Class:$rs2, Op2Class:$rs1,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy),
+ []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1422,9 +1429,10 @@ class VPseudoTiedBinaryMask<VReg RetClass,
string Constraint,
bits<2> TargetConstraintType = 1> :
RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$passthru,
- Op2Class:$rs1,
- VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []> {
+ (ins GetVRegNoV0<RetClass>.R:$passthru,
+ Op2Class:$rs1,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy),
+ []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1443,11 +1451,11 @@ class VPseudoTiedBinaryMaskRoundingMode<VReg RetClass,
string Constraint,
bits<2> TargetConstraintType = 1> :
RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$passthru,
- Op2Class:$rs1,
- VMaskOp:$vm,
- vec_rm:$rm,
- AVL:$vl, sew:$sew, vec_policy:$policy), []> {
+ (ins GetVRegNoV0<RetClass>.R:$passthru,
+ Op2Class:$rs1,
+ VMaskOp:$vm,
+ vec_rm:$rm,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1472,11 +1480,11 @@ class VPseudoBinaryCarry<VReg RetClass,
string Constraint,
bits<2> TargetConstraintType = 1> :
RISCVVPseudo<(outs RetClass:$rd),
- !if(CarryIn,
- (ins Op1Class:$rs2, Op2Class:$rs1,
- VMV0:$carry, AVL:$vl, sew:$sew),
- (ins Op1Class:$rs2, Op2Class:$rs1,
- AVL:$vl, sew:$sew)), []> {
+ !if(CarryIn,
+ (ins Op1Class:$rs2, Op2Class:$rs1,
+ VMV0:$carry, AVL:$vl, sew:$sew),
+ (ins Op1Class:$rs2, Op2Class:$rs1,
+ AVL:$vl, sew:$sew)), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1493,8 +1501,8 @@ class VPseudoTiedBinaryCarryIn<VReg RetClass,
LMULInfo MInfo,
bits<2> TargetConstraintType = 1> :
RISCVVPseudo<(outs RetClass:$rd),
- (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1,
- VMV0:$carry, AVL:$vl, sew:$sew), []> {
+ (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1,
+ VMV0:$carry, AVL:$vl, sew:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1511,8 +1519,8 @@ class VPseudoTernaryNoMask<VReg RetClass,
DAGOperand Op2Class,
string Constraint> :
RISCVVPseudo<(outs RetClass:$rd),
- (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
- AVL:$vl, sew:$sew), []> {
+ (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
+ AVL:$vl, sew:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1527,8 +1535,8 @@ class VPseudoTernaryNoMaskWithPolicy<VReg RetClass,
string Constraint = "",
bits<2> TargetConstraintType = 1> :
RISCVVPseudo<(outs RetClass:$rd),
- (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
- AVL:$vl, sew:$sew, vec_policy:$policy), []> {
+ (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1545,8 +1553,9 @@ class VPseudoTernaryNoMaskWithPolicyRoundingMode<VReg RetClass,
string Constraint = "",
bits<2> TargetConstraintType = 1> :
RISCVVPseudo<(outs RetClass:$rd),
- (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
- vec_rm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy), []> {
+ (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
+ vec_rm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy),
+ []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1564,8 +1573,8 @@ class VPseudoUSSegLoadNoMask<VReg RetClass,
int EEW,
bits<4> NF> :
RISCVVPseudo<(outs RetClass:$rd),
- (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$vl,
- sew:$sew, vec_policy:$policy), []>,
+ (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$vl,
+ sew:$sew, vec_policy:$policy), []>,
RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
@@ -1580,8 +1589,9 @@ class VPseudoUSSegLoadMask<VReg RetClass,
int EEW,
bits<4> NF> :
RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$passthru, GPRMemZeroOffset:$rs1,
- VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
+ (ins GetVRegNoV0<RetClass>.R:$passthru,
+ GPRMemZeroOffset:$rs1, VMaskOp:$vm, AVL:$vl, sew:$sew,
+ vec_policy:$policy), []>,
RISCVVLSEG<NF, /*Masked*/1, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
@@ -1598,8 +1608,8 @@ class VPseudoUSSegLoadFFNoMask<VReg RetClass,
int EEW,
bits<4> NF> :
RISCVVPseudo<(outs RetClass:$rd, GPR:$vl),
- (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$avl,
- sew:$sew, vec_policy:$policy), []>,
+ (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$avl,
+ sew:$sew, vec_policy:$policy), []>,
RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
@@ -1614,8 +1624,9 @@ class VPseudoUSSegLoadFFMask<VReg RetClass,
int EEW,
bits<4> NF> :
RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl),
- (ins GetVRegNoV0<RetClass>.R:$passthru, GPRMemZeroOffset:$rs1,
- VMaskOp:$vm, AVL:$avl, sew:$sew, vec_policy:$policy), []>,
+ (ins GetVRegNoV0<RetClass>.R:$passthru,
+ GPRMemZeroOffset:$rs1, VMaskOp:$vm, AVL:$avl, sew:$sew,
+ vec_policy:$policy), []>,
RISCVVLSEG<NF, /*Masked*/1, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
@@ -1632,8 +1643,8 @@ class VPseudoSSegLoadNoMask<VReg RetClass,
int EEW,
bits<4> NF> :
RISCVVPseudo<(outs RetClass:$rd),
- (ins RetClass:$passthru, GPRMemZeroOffset:$rs1, GPR:$offset, AVL:$vl,
- sew:$sew, vec_policy:$policy), []>,
+ (ins RetClass:$passthru, GPRMemZeroOffset:$rs1, GPR:$offset,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVLSEG<NF, /*Masked*/0, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
@@ -1648,9 +1659,9 @@ class VPseudoSSegLoadMask<VReg RetClass,
int EEW,
bits<4> NF> :
RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$passthru, GPRMemZeroOffset:$rs1,
- GPR:$offset, VMaskOp:$vm, AVL:$vl, sew:$sew,
- vec_policy:$policy), []>,
+ (ins GetVRegNoV0<RetClass>.R:$passthru,
+ GPRMemZeroOffset:$rs1, GPR:$offset, VMaskOp:$vm,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVLSEG<NF, /*Masked*/1, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
let mayStore = 0;
@@ -1670,8 +1681,9 @@ class VPseudoISegLoadNoMask<VReg RetClass,
bits<4> NF,
bit Ordered> :
RISCVVPseudo<(outs RetClass:$rd),
- (ins RetClass:$passthru, GPRMemZeroOffset:$rs1, IdxClass:$offset, AVL:$vl,
- sew:$sew, vec_policy:$policy), []>,
+ (ins RetClass:$passthru, GPRMemZeroOffset:$rs1,
+ IdxClass:$offset, AVL:$vl, sew:$sew,
+ vec_policy:$policy), []>,
RISCVVLXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 1;
let mayStore = 0;
@@ -1691,9 +1703,9 @@ class VPseudoISegLoadMask<VReg RetClass,
bits<4> NF,
bit Ordered> :
RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$passthru, GPRMemZeroOffset:$rs1,
- IdxClass:$offset, VMaskOp:$vm, AVL:$vl, sew:$sew,
- vec_policy:$policy), []>,
+ (ins GetVRegNoV0<RetClass>.R:$passthru,
+ GPRMemZeroOffset:$rs1, IdxClass:$offset, VMaskOp:$vm,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVLXSEG<NF, /*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 1;
let mayStore = 0;
@@ -1712,7 +1724,8 @@ class VPseudoUSSegStoreNoMask<VReg ValClass,
int EEW,
bits<4> NF> :
RISCVVPseudo<(outs),
- (ins ValClass:$rd, GPRMemZeroOffset:$rs1, AVL:$vl, sew:$sew), []>,
+ (ins ValClass:$rd, GPRMemZeroOffset:$rs1, AVL:$vl, sew:$sew),
+ []>,
RISCVVSSEG<NF, /*Masked*/0, /*Strided*/0, !logtwo(EEW), VLMul> {
let mayLoad = 0;
let mayStore = 1;
@@ -1725,8 +1738,8 @@ class VPseudoUSSegStoreMask<VReg ValClass,
int EEW,
bits<4> NF> :
RISCVVPseudo<(outs),
- (ins ValClass:$rd, GPRMemZeroOffset:$rs1,
- VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
+ (ins ValClass:$rd, GPRMemZeroOffset:$rs1,
+ VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
RISCVVSSEG<NF, /*Masked*/1, /*Strided*/0, !logtwo(EEW), VLMul> {
let mayLoad = 0;
let mayStore = 1;
@@ -1740,8 +1753,8 @@ class VPseudoSSegStoreNoMask<VReg ValClass,
int EEW,
bits<4> NF> :
RISCVVPseudo<(outs),
- (ins ValClass:$rd, GPRMemZeroOffset:$rs1, GPR:$offset,
- AVL:$vl, sew:$sew), []>,
+ (ins ValClass:$rd, GPRMemZeroOffset:$rs1, GPR:$offset,
+ AVL:$vl, sew:$sew), []>,
RISCVVSSEG<NF, /*Masked*/0, /*Strided*/1, !logtwo(EEW), VLMul> {
let mayLoad = 0;
let mayStore = 1;
@@ -1754,8 +1767,8 @@ class VPseudoSSegStoreMask<VReg ValClass,
int EEW,
bits<4> NF> :
RISCVVPseudo<(outs),
- (ins ValClass:$rd, GPRMemZeroOffset:$rs1, GPR: $offset,
- VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
+ (ins ValClass:$rd, GPRMemZeroOffset:$rs1, GPR: $offset,
+ VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
RISCVVSSEG<NF, /*Masked*/1, /*Strided*/1, !logtwo(EEW), VLMul> {
let mayLoad = 0;
let mayStore = 1;
@@ -1772,8 +1785,8 @@ class VPseudoISegStoreNoMask<VReg ValClass,
bits<4> NF,
bit Ordered> :
RISCVVPseudo<(outs),
- (ins ValClass:$rd, GPRMemZeroOffset:$rs1, IdxClass: $index,
- AVL:$vl, sew:$sew), []>,
+ (ins ValClass:$rd, GPRMemZeroOffset:$rs1, IdxClass: $index,
+ AVL:$vl, sew:$sew), []>,
RISCVVSXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 0;
let mayStore = 1;
@@ -1789,8 +1802,8 @@ class VPseudoISegStoreMask<VReg ValClass,
bits<4> NF,
bit Ordered> :
RISCVVPseudo<(outs),
- (ins ValClass:$rd, GPRMemZeroOffset:$rs1, IdxClass: $index,
- VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
+ (ins ValClass:$rd, GPRMemZeroOffset:$rs1, IdxClass: $index,
+ VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
RISCVVSXSEG<NF, /*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 0;
let mayStore = 1;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
index 786183421feed..1bb67f4cc7c59 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
@@ -449,9 +449,9 @@ class NDSRVInstVLN<bits<5> funct5, string opcodestr>
class VPseudoVLN8NoMask<VReg RetClass, bit U> :
RISCVVPseudo<(outs RetClass:$rd),
- (ins RetClass:$dest,
- GPRMemZeroOffset:$rs1,
- AVL:$vl, sew:$sew, vec_policy:$policy), []>,
+ (ins RetClass:$dest,
+ GPRMemZeroOffset:$rs1,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVNDSVLN</*Masked*/0, /*Unsigned*/U, !logtwo(8), VLMul> {
let mayLoad = 1;
let mayStore = 0;
@@ -464,9 +464,10 @@ class VPseudoVLN8NoMask<VReg RetClass, bit U> :
class VPseudoVLN8Mask<VReg RetClass, bit U> :
RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$passthru,
- GPRMemZeroOffset:$rs1,
- VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
+ (ins GetVRegNoV0<RetClass>.R:$passthru,
+ GPRMemZeroOffset:$rs1,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy),
+ []>,
RISCVNDSVLN</*Masked*/1, /*Unsigned*/U, !logtwo(8), VLMul> {
let mayLoad = 1;
let mayStore = 0;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
index 5395f3b3d52be..ebcf079f300b3 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
@@ -154,16 +154,17 @@ foreach m = MxList in {
let VLMul = m.value in {
let BaseInstr = RI_VEXTRACT in
def PseudoRI_VEXTRACT_ # mx :
- RISCVVPseudo<(outs GPR:$rd), (ins m.vrclass:$rs2, uimm5:$idx, ixlenimm:$sew),
- []>;
+ RISCVVPseudo<(outs GPR:$rd),
+ (ins m.vrclass:$rs2, uimm5:$idx, ixlenimm:$sew),
+ []>;
let HasVLOp = 1, BaseInstr = RI_VINSERT, HasVecPolicyOp = 1,
Constraints = "$rd = $rs1" in
def PseudoRI_VINSERT_ # mx :
RISCVVPseudo<(outs m.vrclass:$rd),
- (ins m.vrclass:$rs1, GPR:$rs2, uimm5:$idx, AVL:$vl,
- ixlenimm:$sew, ixlenimm:$policy),
- []>;
+ (ins m.vrclass:$rs1, GPR:$rs2, uimm5:$idx, AVL:$vl,
+ ixlenimm:$sew, ixlenimm:$policy),
+ []>;
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
index 87e0b1b93bb0f..a47dfe363c21e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
@@ -244,8 +244,8 @@ let Predicates = [HasVendorXSfvfnrclipxfqf], DecoderNamespace = "XSfvector",
class VPseudoVC_X<Operand OpClass, DAGOperand RS1Class> :
RISCVVPseudo<(outs),
- (ins OpClass:$op1, payload5:$rs2, payload5:$rd, RS1Class:$r1,
- AVL:$vl, sew:$sew), []> {
+ (ins OpClass:$op1, payload5:$rs2, payload5:$rd, RS1Class:$r1,
+ AVL:$vl, sew:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let HasVLOp = 1;
@@ -255,8 +255,8 @@ class VPseudoVC_X<Operand OpClass, DAGOperand RS1Class> :
class VPseudoVC_XV<Operand OpClass, VReg RS2Class, DAGOperand RS1Class> :
RISCVVPseudo<(outs),
- (ins OpClass:$op1, payload5:$rd, RS2Class:$rs2, RS1Class:$r1,
- AVL:$vl, sew:$sew), []> {
+ (ins OpClass:$op1, payload5:$rd, RS2Class:$rs2, RS1Class:$r1,
+ AVL:$vl, sew:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let HasVLOp = 1;
@@ -267,8 +267,8 @@ class VPseudoVC_XV<Operand OpClass, VReg RS2Class, DAGOperand RS1Class> :
class VPseudoVC_XVV<Operand OpClass, VReg RDClass, VReg RS2Class,
DAGOperand RS1Class> :
RISCVVPseudo<(outs),
- (ins OpClass:$op1, RDClass:$rd, RS2Class:$rs2, RS1Class:$r1,
- AVL:$vl, sew:$sew), []> {
+ (ins OpClass:$op1, RDClass:$rd, RS2Class:$rs2, RS1Class:$r1,
+ AVL:$vl, sew:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let HasVLOp = 1;
@@ -278,8 +278,8 @@ class VPseudoVC_XVV<Operand OpClass, VReg RDClass, VReg RS2Class,
class VPseudoVC_V_X<Operand OpClass, VReg RDClass, DAGOperand RS1Class> :
RISCVVPseudo<(outs RDClass:$rd),
- (ins OpClass:$op1, payload5:$rs2, RS1Class:$r1,
- AVL:$vl, sew:$sew), []> {
+ (ins OpClass:$op1, payload5:$rs2, RS1Class:$r1,
+ AVL:$vl, sew:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let HasVLOp = 1;
@@ -290,8 +290,8 @@ class VPseudoVC_V_X<Operand OpClass, VReg RDClass, DAGOperand RS1Class> :
class VPseudoVC_V_XV<Operand OpClass, VReg RDClass, VReg RS2Class,
DAGOperand RS1Class> :
RISCVVPseudo<(outs RDClass:$rd),
- (ins OpClass:$op1, RS2Class:$rs2, RS1Class:$r1,
- AVL:$vl, sew:$sew), []> {
+ (ins OpClass:$op1, RS2Class:$rs2, RS1Class:$r1,
+ AVL:$vl, sew:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let HasVLOp = 1;
@@ -302,8 +302,8 @@ class VPseudoVC_V_XV<Operand OpClass, VReg RDClass, VReg RS2Class,
class VPseudoVC_V_XVV<Operand OpClass, VReg RDClass, VReg RS2Class,
DAGOperand RS1Class> :
RISCVVPseudo<(outs RDClass:$rd),
- (ins OpClass:$op1, RDClass:$rs3, RS2Class:$rs2, RS1Class:$r1,
- AVL:$vl, sew:$sew), []> {
+ (ins OpClass:$op1, RDClass:$rs3, RS2Class:$rs2, RS1Class:$r1,
+ AVL:$vl, sew:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let HasVLOp = 1;
>From 2590e748be17d5a081a0262f9009105f27a74730 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Tue, 22 Jul 2025 15:52:47 +0800
Subject: [PATCH 3/3] Don't copy over TSFlags
---
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 4 ----
llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 6 +++++-
llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp | 15 ++++++++-------
3 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 1b6db9b664771..abc575eb40c0d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -550,10 +550,6 @@ class RISCVVPseudo<dag outs, dag ins, list<dag> pattern, string opcodestr = "",
// SEW = 0 is used to denote that the Pseudo is not SEW specific (or unknown).
bits<8> SEW = 0;
bit IncludeInInversePseudoTable = 1;
-
- // Set common TSFlags in RVInst from the base instruction.
- let ElementsDependOn = !cast<RVInst>(BaseInstr).ElementsDependOn;
- let DestEEW = !cast<RVInst>(BaseInstr).DestEEW;
}
// The actual table.
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index ee63e19350a9f..15bd3466373a7 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -33,6 +33,7 @@ namespace {
class RISCVVLOptimizer : public MachineFunctionPass {
const MachineRegisterInfo *MRI;
const MachineDominatorTree *MDT;
+ const TargetInstrInfo *TII;
public:
static char ID;
@@ -1291,7 +1292,8 @@ bool RISCVVLOptimizer::isCandidate(const MachineInstr &MI) const {
return false;
}
- assert(!RISCVII::elementsDependOnVL(MI.getDesc().TSFlags) &&
+ assert(!RISCVII::elementsDependOnVL(
+ TII->get(RISCV::getRVVMCOpcode(MI.getOpcode())).TSFlags) &&
"Instruction shouldn't be supported if elements depend on VL");
assert(MI.getOperand(0).isReg() &&
@@ -1495,6 +1497,8 @@ bool RISCVVLOptimizer::runOnMachineFunction(MachineFunction &MF) {
if (!ST.hasVInstructions())
return false;
+ TII = ST.getInstrInfo();
+
// For each instruction that defines a vector, compute what VL its
// downstream users demand.
for (MachineBasicBlock *MBB : post_order(&MF)) {
diff --git a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
index b249795dfe52d..84ef53985484f 100644
--- a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
@@ -91,7 +91,8 @@ bool RISCVVectorPeephole::hasSameEEW(const MachineInstr &User,
User.getOperand(RISCVII::getSEWOpNum(User.getDesc())).getImm();
unsigned SrcLog2SEW =
Src.getOperand(RISCVII::getSEWOpNum(Src.getDesc())).getImm();
- unsigned SrcLog2EEW = RISCV::getDestLog2EEW(Src.getDesc(), SrcLog2SEW);
+ unsigned SrcLog2EEW = RISCV::getDestLog2EEW(
+ TII->get(RISCV::getRVVMCOpcode(Src.getOpcode())), SrcLog2SEW);
return SrcLog2EEW == UserLog2SEW;
}
@@ -169,8 +170,8 @@ bool RISCVVectorPeephole::tryToReduceVL(MachineInstr &MI) const {
if (!hasSameEEW(MI, *Src))
continue;
- bool ElementsDependOnVL =
- RISCVII::elementsDependOnVL(Src->getDesc().TSFlags);
+ bool ElementsDependOnVL = RISCVII::elementsDependOnVL(
+ TII->get(RISCV::getRVVMCOpcode(Src->getOpcode())).TSFlags);
if (ElementsDependOnVL || Src->mayRaiseFPException())
continue;
@@ -759,11 +760,11 @@ bool RISCVVectorPeephole::foldVMergeToMask(MachineInstr &MI) const {
else
return false;
- if (RISCVII::elementsDependOnVL(True.getDesc().TSFlags) &&
- !TrueVL.isIdenticalTo(MinVL))
+ unsigned RVVTSFlags =
+ TII->get(RISCV::getRVVMCOpcode(True.getOpcode())).TSFlags;
+ if (RISCVII::elementsDependOnVL(RVVTSFlags) && !TrueVL.isIdenticalTo(MinVL))
return false;
- if (RISCVII::elementsDependOnMask(True.getDesc().TSFlags) &&
- !isAllOnesMask(Mask))
+ if (RISCVII::elementsDependOnMask(RVVTSFlags) && !isAllOnesMask(Mask))
return false;
// Use a tumu policy, relaxing it to tail agnostic provided that the passthru
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