[llvm] [RISCV] Handled the uimm9 offset while FrameIndex folding. (PR #149303)
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Mon Jul 21 23:47:14 PDT 2025
https://github.com/ukalappa-mips updated https://github.com/llvm/llvm-project/pull/149303
>From 16e7516a04a1f93ed9a891720e022ed5e7388b99 Mon Sep 17 00:00:00 2001
From: Umesh Kalappa <ukalappa.mips at gmail.com>
Date: Thu, 17 Jul 2025 13:14:54 +0000
Subject: [PATCH 1/3] Handle and honour the uimm9 offset for mips prefetch.
---
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 8 ++--
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 8 ++++
llvm/test/CodeGen/RISCV/xmips-cbop.ll | 44 +++++++++++++++++++++
3 files changed, 56 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 0f948b22759fe..ddba47b1975c7 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2942,8 +2942,8 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
/// Similar to SelectAddrRegImm, except that the offset is restricted to uimm9.
bool RISCVDAGToDAGISel::SelectAddrRegImm9(SDValue Addr, SDValue &Base,
SDValue &Offset) {
- // FIXME: Support FrameIndex. Need to teach eliminateFrameIndex that only
- // a 9-bit immediate can be folded.
+ if (SelectAddrFrameIndex(Addr, Base, Offset))
+ return true;
SDLoc DL(Addr);
MVT VT = Addr.getSimpleValueType();
@@ -2953,8 +2953,8 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm9(SDValue Addr, SDValue &Base,
if (isUInt<9>(CVal)) {
Base = Addr.getOperand(0);
- // FIXME: Support FrameIndex. Need to teach eliminateFrameIndex that only
- // a 9-bit immediate can be folded.
+ if (auto *FIN = dyn_cast<FrameIndexSDNode>(Base))
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), VT);
Offset = CurDAG->getSignedTargetConstant(CVal, DL, VT);
return true;
}
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 540412366026b..4b9ba0f33276e 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -573,6 +573,9 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
int64_t Val = Offset.getFixed();
int64_t Lo12 = SignExtend64<12>(Val);
unsigned Opc = MI.getOpcode();
+ int64_t Imm9Val = SignExtend64<9>(Val);
+ auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
+
if (Opc == RISCV::ADDI && !isInt<12>(Val)) {
// We chose to emit the canonical immediate sequence rather than folding
// the offset into the using add under the theory that doing so doesn't
@@ -585,6 +588,11 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
(Lo12 & 0b11111) != 0) {
// Prefetch instructions require the offset to be 32 byte aligned.
MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
+ } else if ((Opc == RISCV::PREFETCH_I || Opc == RISCV::PREFETCH_R ||
+ Opc == RISCV::PREFETCH_W) &&
+ Subtarget.hasVendorXMIPSCBOP() && !isUInt<9>(Imm9Val)) {
+ // MIPS Prefetch instructions require the offset to be 9 bits encoded.
+ MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
} else if ((Opc == RISCV::PseudoRV32ZdinxLD ||
Opc == RISCV::PseudoRV32ZdinxSD) &&
Lo12 >= 2044) {
diff --git a/llvm/test/CodeGen/RISCV/xmips-cbop.ll b/llvm/test/CodeGen/RISCV/xmips-cbop.ll
index cbbd1de13192c..0cfe3e3f0ab7c 100644
--- a/llvm/test/CodeGen/RISCV/xmips-cbop.ll
+++ b/llvm/test/CodeGen/RISCV/xmips-cbop.ll
@@ -49,3 +49,47 @@ define void @prefetch_inst_read(ptr noundef %ptr) nounwind {
tail call void @llvm.prefetch.p0(ptr nonnull %arrayidx, i32 0, i32 0, i32 0)
ret void
}
+
+define void @prefetch_frameindex_test_neg() nounwind {
+; RV32XMIPSPREFETCH-LABEL: prefetch_frameindex_test_neg:
+; RV32XMIPSPREFETCH: # %bb.0:
+; RV32XMIPSPREFETCH-NEXT: addi sp, sp, -512
+; RV32XMIPSPREFETCH-NEXT: addi a0, sp, -32
+; RV32XMIPSPREFETCH-NEXT: mips.pref 8, 0(a0)
+; RV32XMIPSPREFETCH-NEXT: addi sp, sp, 512
+; RV32XMIPSPREFETCH-NEXT: ret
+;
+; RV64XMIPSPREFETCH-LABEL: prefetch_frameindex_test_neg:
+; RV64XMIPSPREFETCH: # %bb.0:
+; RV64XMIPSPREFETCH-NEXT: addi sp, sp, -512
+; RV64XMIPSPREFETCH-NEXT: addi a0, sp, -32
+; RV64XMIPSPREFETCH-NEXT: mips.pref 8, 0(a0)
+; RV64XMIPSPREFETCH-NEXT: addi sp, sp, 512
+; RV64XMIPSPREFETCH-NEXT: ret
+ %data = alloca [128 x i32], align 4
+ %base = bitcast ptr %data to ptr
+ %ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 -8
+ call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @prefetch_frameindex_test() nounwind {
+; RV32XMIPSPREFETCH-LABEL: prefetch_frameindex_test:
+; RV32XMIPSPREFETCH: # %bb.0:
+; RV32XMIPSPREFETCH-NEXT: addi sp, sp, -512
+; RV32XMIPSPREFETCH-NEXT: mips.pref 8, 32(sp)
+; RV32XMIPSPREFETCH-NEXT: addi sp, sp, 512
+; RV32XMIPSPREFETCH-NEXT: ret
+;
+; RV64XMIPSPREFETCH-LABEL: prefetch_frameindex_test:
+; RV64XMIPSPREFETCH: # %bb.0:
+; RV64XMIPSPREFETCH-NEXT: addi sp, sp, -512
+; RV64XMIPSPREFETCH-NEXT: mips.pref 8, 32(sp)
+; RV64XMIPSPREFETCH-NEXT: addi sp, sp, 512
+; RV64XMIPSPREFETCH-NEXT: ret
+ %data = alloca [128 x i32], align 4
+ %base = bitcast ptr %data to ptr
+ %ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 8
+ call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
+ ret void
+}
>From e8177b22f1fd4bfe50774e122b9b8cbf1e391c16 Mon Sep 17 00:00:00 2001
From: Umesh Kalappa <ukalappa.mips at gmail.com>
Date: Fri, 18 Jul 2025 10:09:18 +0000
Subject: [PATCH 2/3] Updated the comments and testcase updated.
---
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 6 ++---
llvm/test/CodeGen/RISCV/xmips-cbop.ll | 26 ++++++++++++++-------
2 files changed, 19 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 4b9ba0f33276e..21c514c16fa0d 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -573,7 +573,6 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
int64_t Val = Offset.getFixed();
int64_t Lo12 = SignExtend64<12>(Val);
unsigned Opc = MI.getOpcode();
- int64_t Imm9Val = SignExtend64<9>(Val);
auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
if (Opc == RISCV::ADDI && !isInt<12>(Val)) {
@@ -588,9 +587,8 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
(Lo12 & 0b11111) != 0) {
// Prefetch instructions require the offset to be 32 byte aligned.
MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
- } else if ((Opc == RISCV::PREFETCH_I || Opc == RISCV::PREFETCH_R ||
- Opc == RISCV::PREFETCH_W) &&
- Subtarget.hasVendorXMIPSCBOP() && !isUInt<9>(Imm9Val)) {
+ } else if (Opc == RISCV::MIPS_PREFETCH && Subtarget.hasVendorXMIPSCBOP() &&
+ !isUInt<9>(Val)) {
// MIPS Prefetch instructions require the offset to be 9 bits encoded.
MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
} else if ((Opc == RISCV::PseudoRV32ZdinxLD ||
diff --git a/llvm/test/CodeGen/RISCV/xmips-cbop.ll b/llvm/test/CodeGen/RISCV/xmips-cbop.ll
index 0cfe3e3f0ab7c..eb83da9635645 100644
--- a/llvm/test/CodeGen/RISCV/xmips-cbop.ll
+++ b/llvm/test/CodeGen/RISCV/xmips-cbop.ll
@@ -53,22 +53,30 @@ define void @prefetch_inst_read(ptr noundef %ptr) nounwind {
define void @prefetch_frameindex_test_neg() nounwind {
; RV32XMIPSPREFETCH-LABEL: prefetch_frameindex_test_neg:
; RV32XMIPSPREFETCH: # %bb.0:
-; RV32XMIPSPREFETCH-NEXT: addi sp, sp, -512
-; RV32XMIPSPREFETCH-NEXT: addi a0, sp, -32
+; RV32XMIPSPREFETCH-NEXT: lui a0, 1
+; RV32XMIPSPREFETCH-NEXT: addi a0, a0, 16
+; RV32XMIPSPREFETCH-NEXT: sub sp, sp, a0
+; RV32XMIPSPREFETCH-NEXT: addi a0, sp, 524
; RV32XMIPSPREFETCH-NEXT: mips.pref 8, 0(a0)
-; RV32XMIPSPREFETCH-NEXT: addi sp, sp, 512
+; RV32XMIPSPREFETCH-NEXT: lui a0, 1
+; RV32XMIPSPREFETCH-NEXT: addi a0, a0, 16
+; RV32XMIPSPREFETCH-NEXT: add sp, sp, a0
; RV32XMIPSPREFETCH-NEXT: ret
;
; RV64XMIPSPREFETCH-LABEL: prefetch_frameindex_test_neg:
; RV64XMIPSPREFETCH: # %bb.0:
-; RV64XMIPSPREFETCH-NEXT: addi sp, sp, -512
-; RV64XMIPSPREFETCH-NEXT: addi a0, sp, -32
+; RV64XMIPSPREFETCH-NEXT: lui a0, 1
+; RV64XMIPSPREFETCH-NEXT: addi a0, a0, 16
+; RV64XMIPSPREFETCH-NEXT: sub sp, sp, a0
+; RV64XMIPSPREFETCH-NEXT: addi a0, sp, 524
; RV64XMIPSPREFETCH-NEXT: mips.pref 8, 0(a0)
-; RV64XMIPSPREFETCH-NEXT: addi sp, sp, 512
+; RV64XMIPSPREFETCH-NEXT: lui a0, 1
+; RV64XMIPSPREFETCH-NEXT: addi a0, a0, 16
+; RV64XMIPSPREFETCH-NEXT: add sp, sp, a0
; RV64XMIPSPREFETCH-NEXT: ret
- %data = alloca [128 x i32], align 4
+ %data = alloca [1024 x i32], align 4
%base = bitcast ptr %data to ptr
- %ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 -8
+ %ptr = getelementptr [127 x i32], ptr %base, i32 0, i32 127
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
}
@@ -87,7 +95,7 @@ define void @prefetch_frameindex_test() nounwind {
; RV64XMIPSPREFETCH-NEXT: mips.pref 8, 32(sp)
; RV64XMIPSPREFETCH-NEXT: addi sp, sp, 512
; RV64XMIPSPREFETCH-NEXT: ret
- %data = alloca [128 x i32], align 4
+ %data = alloca [128 x i32], align 4
%base = bitcast ptr %data to ptr
%ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 8
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
>From ed463e001c2e592b950246f86a48d754e88a8468 Mon Sep 17 00:00:00 2001
From: Umesh Kalappa <ukalappa.mips at gmail.com>
Date: Tue, 22 Jul 2025 06:46:09 +0000
Subject: [PATCH 3/3] Removed the redundant checks.
---
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 3 +--
llvm/test/CodeGen/RISCV/xmips-cbop.ll | 4 ++--
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 21c514c16fa0d..0c51b08071949 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -587,8 +587,7 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
(Lo12 & 0b11111) != 0) {
// Prefetch instructions require the offset to be 32 byte aligned.
MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
- } else if (Opc == RISCV::MIPS_PREFETCH && Subtarget.hasVendorXMIPSCBOP() &&
- !isUInt<9>(Val)) {
+ } else if (Opc == RISCV::MIPS_PREFETCH && !isUInt<9>(Val)) {
// MIPS Prefetch instructions require the offset to be 9 bits encoded.
MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
} else if ((Opc == RISCV::PseudoRV32ZdinxLD ||
diff --git a/llvm/test/CodeGen/RISCV/xmips-cbop.ll b/llvm/test/CodeGen/RISCV/xmips-cbop.ll
index eb83da9635645..87d2bfb81a95a 100644
--- a/llvm/test/CodeGen/RISCV/xmips-cbop.ll
+++ b/llvm/test/CodeGen/RISCV/xmips-cbop.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=riscv32 -mattr=+xmipscbop -mattr=+m -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+xmipscbop -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32XMIPSPREFETCH
-; RUN: llc -mtriple=riscv64 -mattr=+xmipscbop -mattr=+m -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+xmipscbop -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64XMIPSPREFETCH
define void @prefetch_data_read(ptr noundef %ptr) nounwind {
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