[llvm] [MISched] Extend overridePostRASchedPolicy to support per-function scheduling direction (PR #149297)
Harrison Hao via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 21 21:46:48 PDT 2025
https://github.com/harrisonGPU updated https://github.com/llvm/llvm-project/pull/149297
>From e9d38f6a352f6fd59e72fa4ee90fdb280798b4fe Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Thu, 17 Jul 2025 20:06:28 +0800
Subject: [PATCH 1/4] [MISched] Extend overridePostRASchedPolicy to support
per-function scheduling direction
---
llvm/include/llvm/CodeGen/TargetSubtargetInfo.h | 2 +-
llvm/lib/CodeGen/MachineScheduler.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVSubtarget.cpp | 4 ++--
llvm/lib/Target/RISCV/RISCVSubtarget.h | 4 ++--
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
index 45e67d80629cb..0e6162aed9df8 100644
--- a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
@@ -241,7 +241,7 @@ class LLVM_ABI TargetSubtargetInfo : public MCSubtargetInfo {
/// Note that some options like tracking register pressure won't take effect
/// in post-ra scheduling.
virtual void overridePostRASchedPolicy(MachineSchedPolicy &Policy,
- unsigned NumRegionInstrs) const {}
+ const MachineFunction &MF) const {}
// Perform target-specific adjustments to the latency of a schedule
// dependency.
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 76cba2949af60..dfea60a84ad45 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -4338,7 +4338,7 @@ void PostGenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
RegionPolicy.OnlyBottomUp = false;
// Allow the subtarget to override default policy.
- MF.getSubtarget().overridePostRASchedPolicy(RegionPolicy, NumRegionInstrs);
+ MF.getSubtarget().overridePostRASchedPolicy(RegionPolicy, MF);
// After subtarget overrides, apply command line options.
if (PostRADirection == MISched::TopDown) {
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index c754de45db7fd..628d82b16b7fe 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -231,8 +231,8 @@ void RISCVSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
Policy.ShouldTrackPressure = true;
}
-void RISCVSubtarget::overridePostRASchedPolicy(MachineSchedPolicy &Policy,
- unsigned NumRegionInstrs) const {
+void RISCVSubtarget::overridePostRASchedPolicy(
+ MachineSchedPolicy &Policy, const MachineFunction &MF) const {
MISched::Direction PostRASchedDirection = getPostRASchedDirection();
if (PostRASchedDirection == MISched::TopDown) {
Policy.OnlyTopDown = true;
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 4f560cca22dff..55f44ac9da1d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -398,8 +398,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
unsigned NumRegionInstrs) const override;
void overridePostRASchedPolicy(MachineSchedPolicy &Policy,
- unsigned NumRegionInstrs) const override;
+ const MachineFunction &MF) const override;
};
-} // End llvm namespace
+} // namespace llvm
#endif
>From cf2392fd967f887e869d6e5ca4e0fa00aa378e27 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Fri, 18 Jul 2025 14:32:54 +0800
Subject: [PATCH 2/4] [MISched] Add MachineBasicBlock.
---
llvm/include/llvm/CodeGen/MachineScheduler.h | 1 +
llvm/include/llvm/CodeGen/TargetSubtargetInfo.h | 5 ++++-
llvm/lib/CodeGen/MachineScheduler.cpp | 7 +++++--
llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 1 +
llvm/lib/Target/AArch64/AArch64Subtarget.h | 1 +
llvm/lib/Target/AMDGPU/GCNSubtarget.cpp | 1 +
llvm/lib/Target/AMDGPU/GCNSubtarget.h | 5 ++---
llvm/lib/Target/PowerPC/PPCSubtarget.cpp | 5 +++--
llvm/lib/Target/PowerPC/PPCSubtarget.h | 1 +
llvm/lib/Target/RISCV/RISCVSubtarget.cpp | 6 ++++--
llvm/lib/Target/RISCV/RISCVSubtarget.h | 4 +++-
11 files changed, 26 insertions(+), 11 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h
index e7a7091acee64..1d37874acd72b 100644
--- a/llvm/include/llvm/CodeGen/MachineScheduler.h
+++ b/llvm/include/llvm/CodeGen/MachineScheduler.h
@@ -65,6 +65,7 @@
//
// void <SubTarget>Subtarget::
// overrideSchedPolicy(MachineSchedPolicy &Policy,
+// const MachineBasicBlock &MBB,
// unsigned NumRegionInstrs) const {
// Policy.<Flag> = true;
// }
diff --git a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
index 0e6162aed9df8..014e7ccaa004c 100644
--- a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
@@ -16,6 +16,7 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MacroFusion.h"
#include "llvm/CodeGen/PBQPRAConstraint.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
@@ -231,6 +232,7 @@ class LLVM_ABI TargetSubtargetInfo : public MCSubtargetInfo {
/// scheduling heuristics (no custom MachineSchedStrategy) to make
/// changes to the generic scheduling policy.
virtual void overrideSchedPolicy(MachineSchedPolicy &Policy,
+ const MachineBasicBlock &MBB,
unsigned NumRegionInstrs) const {}
/// Override generic post-ra scheduling policy within a region.
@@ -241,7 +243,8 @@ class LLVM_ABI TargetSubtargetInfo : public MCSubtargetInfo {
/// Note that some options like tracking register pressure won't take effect
/// in post-ra scheduling.
virtual void overridePostRASchedPolicy(MachineSchedPolicy &Policy,
- const MachineFunction &MF) const {}
+ const MachineBasicBlock &MBB,
+ unsigned NumRegionInstrs) const {}
// Perform target-specific adjustments to the latency of a schedule
// dependency.
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index dfea60a84ad45..80c238417d727 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -3703,6 +3703,7 @@ void GenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
MachineBasicBlock::iterator End,
unsigned NumRegionInstrs) {
const MachineFunction &MF = *Begin->getMF();
+ const MachineBasicBlock &MBB = *Begin->getParent();
const TargetLowering *TLI = MF.getSubtarget().getTargetLowering();
// Avoid setting up the register pressure tracker for small regions to save
@@ -3725,7 +3726,7 @@ void GenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
RegionPolicy.OnlyBottomUp = true;
// Allow the subtarget to override default policy.
- MF.getSubtarget().overrideSchedPolicy(RegionPolicy, NumRegionInstrs);
+ MF.getSubtarget().overrideSchedPolicy(RegionPolicy, MBB, NumRegionInstrs);
// After subtarget overrides, apply command line options.
if (!EnableRegPressure) {
@@ -4331,6 +4332,7 @@ void PostGenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
MachineBasicBlock::iterator End,
unsigned NumRegionInstrs) {
const MachineFunction &MF = *Begin->getMF();
+ const MachineBasicBlock &MBB = *Begin->getParent();
// Default to top-down because it was implemented first and existing targets
// expect that behavior by default.
@@ -4338,7 +4340,8 @@ void PostGenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
RegionPolicy.OnlyBottomUp = false;
// Allow the subtarget to override default policy.
- MF.getSubtarget().overridePostRASchedPolicy(RegionPolicy, MF);
+ MF.getSubtarget().overridePostRASchedPolicy(RegionPolicy, MBB,
+ NumRegionInstrs);
// After subtarget overrides, apply command line options.
if (PostRADirection == MISched::TopDown) {
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
index 2409cc862f21c..26dadebbe6302 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -534,6 +534,7 @@ unsigned AArch64Subtarget::classifyGlobalFunctionReference(
}
void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
+ const MachineBasicBlock &MBB,
unsigned NumRegionInstrs) const {
// LNT run (at least on Cyclone) showed reasonably significant gains for
// bi-directional scheduling. 253.perlbmk.
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index 154db3c074f71..ce31de73160c4 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -343,6 +343,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
}
void overrideSchedPolicy(MachineSchedPolicy &Policy,
+ const MachineBasicBlock &MBB,
unsigned NumRegionInstrs) const override;
void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx,
SDep &Dep,
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
index 7b8f0f44cbe2c..6b75da37f1d5f 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
@@ -324,6 +324,7 @@ bool GCNSubtarget::zeroesHigh16BitsOfDest(unsigned Opcode) const {
}
void GCNSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
+ const MachineBasicBlock &MBB,
unsigned NumRegionInstrs) const {
// Track register pressure so the scheduler can try to decrease
// pressure once register usage is above the threshold defined by
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index 68430526dba26..5265ae70d8378 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -1015,11 +1015,10 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
static bool hasHalfRate64Ops(const TargetSubtargetInfo &STI);
// XXX - Why is this here if it isn't in the default pass set?
- bool enableEarlyIfConversion() const override {
- return true;
- }
+ bool enableEarlyIfConversion() const override { return true; }
void overrideSchedPolicy(MachineSchedPolicy &Policy,
+ const MachineBasicBlock &MBB,
unsigned NumRegionInstrs) const override;
void mirFileLoaded(MachineFunction &MF) const override;
diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
index 75a0272af7c31..0d88495de3550 100644
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -166,11 +166,12 @@ PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const
void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
CriticalPathRCs.clear();
- CriticalPathRCs.push_back(isPPC64() ?
- &PPC::G8RCRegClass : &PPC::GPRCRegClass);
+ CriticalPathRCs.push_back(isPPC64() ? &PPC::G8RCRegClass
+ : &PPC::GPRCRegClass);
}
void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
+ const MachineBasicBlock &MBB,
unsigned NumRegionInstrs) const {
// The GenericScheduler that we use defaults to scheduling bottom up only.
// We want to schedule from both the top and the bottom and so we set
diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.h b/llvm/lib/Target/PowerPC/PPCSubtarget.h
index 9a97d1aa4dab0..e45e17b3968b9 100644
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -240,6 +240,7 @@ class PPCSubtarget : public PPCGenSubtargetInfo {
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
void overrideSchedPolicy(MachineSchedPolicy &Policy,
+ const MachineBasicBlock &MBB,
unsigned NumRegionInstrs) const override;
bool useAA() const override;
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index 628d82b16b7fe..2162445721df9 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -216,6 +216,7 @@ unsigned RISCVSubtarget::getMinimumJumpTableEntries() const {
}
void RISCVSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
+ const MachineBasicBlock &MBB,
unsigned NumRegionInstrs) const {
// Do bidirectional scheduling since it provides a more balanced scheduling
// leading to better performance. This will increase compile time.
@@ -231,8 +232,9 @@ void RISCVSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
Policy.ShouldTrackPressure = true;
}
-void RISCVSubtarget::overridePostRASchedPolicy(
- MachineSchedPolicy &Policy, const MachineFunction &MF) const {
+void RISCVSubtarget::overridePostRASchedPolicy(MachineSchedPolicy &Policy,
+ const MachineBasicBlock &MBB,
+ unsigned NumRegionInstrs) const {
MISched::Direction PostRASchedDirection = getPostRASchedDirection();
if (PostRASchedDirection == MISched::TopDown) {
Policy.OnlyTopDown = true;
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 55f44ac9da1d1..fffc7e3ef23df 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -395,10 +395,12 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
}
void overrideSchedPolicy(MachineSchedPolicy &Policy,
+ const MachineBasicBlock &MBB,
unsigned NumRegionInstrs) const override;
void overridePostRASchedPolicy(MachineSchedPolicy &Policy,
- const MachineFunction &MF) const override;
+ const MachineBasicBlock &MBB,
+ unsigned NumRegionInstrs) const override;
};
} // namespace llvm
>From ed803504672303d08c37fdad147706625de59245 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Sat, 19 Jul 2025 05:00:33 +0000
Subject: [PATCH 3/4] Update for comments.
---
llvm/include/llvm/CodeGen/TargetSubtargetInfo.h | 2 +-
llvm/lib/Target/AMDGPU/GCNSubtarget.h | 4 +++-
llvm/lib/Target/PowerPC/PPCSubtarget.cpp | 4 ++--
llvm/lib/Target/RISCV/RISCVSubtarget.h | 2 +-
4 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
index 014e7ccaa004c..258719752366a 100644
--- a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
@@ -16,7 +16,6 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
-#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MacroFusion.h"
#include "llvm/CodeGen/PBQPRAConstraint.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
@@ -31,6 +30,7 @@ namespace llvm {
class APInt;
class MachineFunction;
+class MachineBasicBlock;
class ScheduleDAGMutation;
class CallLowering;
class GlobalValue;
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index 5265ae70d8378..7b7efc4109d28 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -1015,7 +1015,9 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
static bool hasHalfRate64Ops(const TargetSubtargetInfo &STI);
// XXX - Why is this here if it isn't in the default pass set?
- bool enableEarlyIfConversion() const override { return true; }
+ bool enableEarlyIfConversion() const override {
+ return true;
+ }
void overrideSchedPolicy(MachineSchedPolicy &Policy,
const MachineBasicBlock &MBB,
diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
index 0d88495de3550..e5d7ce082c645 100644
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -166,8 +166,8 @@ PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const
void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
CriticalPathRCs.clear();
- CriticalPathRCs.push_back(isPPC64() ? &PPC::G8RCRegClass
- : &PPC::GPRCRegClass);
+ CriticalPathRCs.push_back(isPPC64() ?
+ &PPC::G8RCRegClass : &PPC::GPRCRegClass);
}
void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index fffc7e3ef23df..325ae72b522ac 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -402,6 +402,6 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
const MachineBasicBlock &MBB,
unsigned NumRegionInstrs) const override;
};
-} // namespace llvm
+} // End llvm namespace
#endif
>From fa4dc0b972a3f42eca47717bcf41943060af7f1f Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Tue, 22 Jul 2025 12:46:06 +0800
Subject: [PATCH 4/4] [MISched] Use Region to replace MBB
---
llvm/include/llvm/CodeGen/MachineScheduler.h | 19 +++++++++++--
.../llvm/CodeGen/TargetSubtargetInfo.h | 9 +++----
llvm/lib/CodeGen/MachineScheduler.cpp | 27 +++----------------
llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 3 +--
llvm/lib/Target/AArch64/AArch64Subtarget.h | 4 +--
llvm/lib/Target/AMDGPU/GCNSubtarget.cpp | 3 +--
llvm/lib/Target/AMDGPU/GCNSubtarget.h | 3 +--
llvm/lib/Target/PowerPC/PPCSubtarget.cpp | 3 +--
llvm/lib/Target/PowerPC/PPCSubtarget.h | 4 +--
llvm/lib/Target/RISCV/RISCVSubtarget.cpp | 8 +++---
llvm/lib/Target/RISCV/RISCVSubtarget.h | 8 +++---
11 files changed, 39 insertions(+), 52 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h
index 1d37874acd72b..efda7eb8ffc8d 100644
--- a/llvm/include/llvm/CodeGen/MachineScheduler.h
+++ b/llvm/include/llvm/CodeGen/MachineScheduler.h
@@ -65,8 +65,7 @@
//
// void <SubTarget>Subtarget::
// overrideSchedPolicy(MachineSchedPolicy &Policy,
-// const MachineBasicBlock &MBB,
-// unsigned NumRegionInstrs) const {
+// const SchedRegion &Region) const {
// Policy.<Flag> = true;
// }
//
@@ -219,6 +218,22 @@ struct MachineSchedPolicy {
MachineSchedPolicy() = default;
};
+/// A region of an MBB for scheduling.
+struct SchedRegion {
+ /// RegionBegin is the first instruction in the scheduling region, and
+ /// RegionEnd is either MBB->end() or the scheduling boundary after the
+ /// last instruction in the scheduling region. These iterators cannot refer
+ /// to instructions outside of the identified scheduling region because
+ /// those may be reordered before scheduling this region.
+ MachineBasicBlock::iterator RegionBegin;
+ MachineBasicBlock::iterator RegionEnd;
+ unsigned NumRegionInstrs;
+
+ SchedRegion(MachineBasicBlock::iterator B, MachineBasicBlock::iterator E,
+ unsigned N)
+ : RegionBegin(B), RegionEnd(E), NumRegionInstrs(N) {}
+};
+
/// MachineSchedStrategy - Interface to the scheduling algorithm used by
/// ScheduleDAGMI.
///
diff --git a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
index 258719752366a..547333cad4f48 100644
--- a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
@@ -30,7 +30,7 @@ namespace llvm {
class APInt;
class MachineFunction;
-class MachineBasicBlock;
+
class ScheduleDAGMutation;
class CallLowering;
class GlobalValue;
@@ -55,6 +55,7 @@ class TargetRegisterClass;
class TargetRegisterInfo;
class TargetSchedModel;
class Triple;
+struct SchedRegion;
//===----------------------------------------------------------------------===//
///
@@ -232,8 +233,7 @@ class LLVM_ABI TargetSubtargetInfo : public MCSubtargetInfo {
/// scheduling heuristics (no custom MachineSchedStrategy) to make
/// changes to the generic scheduling policy.
virtual void overrideSchedPolicy(MachineSchedPolicy &Policy,
- const MachineBasicBlock &MBB,
- unsigned NumRegionInstrs) const {}
+ const SchedRegion &Region) const {}
/// Override generic post-ra scheduling policy within a region.
///
@@ -243,8 +243,7 @@ class LLVM_ABI TargetSubtargetInfo : public MCSubtargetInfo {
/// Note that some options like tracking register pressure won't take effect
/// in post-ra scheduling.
virtual void overridePostRASchedPolicy(MachineSchedPolicy &Policy,
- const MachineBasicBlock &MBB,
- unsigned NumRegionInstrs) const {}
+ const SchedRegion &Region) const {}
// Perform target-specific adjustments to the latency of a schedule
// dependency.
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 80c238417d727..9d5c39ce7ae76 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -771,24 +771,6 @@ static bool isSchedBoundary(MachineBasicBlock::iterator MI,
MI->isFakeUse();
}
-/// A region of an MBB for scheduling.
-namespace {
-struct SchedRegion {
- /// RegionBegin is the first instruction in the scheduling region, and
- /// RegionEnd is either MBB->end() or the scheduling boundary after the
- /// last instruction in the scheduling region. These iterators cannot refer
- /// to instructions outside of the identified scheduling region because
- /// those may be reordered before scheduling this region.
- MachineBasicBlock::iterator RegionBegin;
- MachineBasicBlock::iterator RegionEnd;
- unsigned NumRegionInstrs;
-
- SchedRegion(MachineBasicBlock::iterator B, MachineBasicBlock::iterator E,
- unsigned N) :
- RegionBegin(B), RegionEnd(E), NumRegionInstrs(N) {}
-};
-} // end anonymous namespace
-
using MBBRegionsVector = SmallVector<SchedRegion, 16>;
static void
@@ -3703,7 +3685,6 @@ void GenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
MachineBasicBlock::iterator End,
unsigned NumRegionInstrs) {
const MachineFunction &MF = *Begin->getMF();
- const MachineBasicBlock &MBB = *Begin->getParent();
const TargetLowering *TLI = MF.getSubtarget().getTargetLowering();
// Avoid setting up the register pressure tracker for small regions to save
@@ -3726,7 +3707,8 @@ void GenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
RegionPolicy.OnlyBottomUp = true;
// Allow the subtarget to override default policy.
- MF.getSubtarget().overrideSchedPolicy(RegionPolicy, MBB, NumRegionInstrs);
+ SchedRegion Region(Begin, End, NumRegionInstrs);
+ MF.getSubtarget().overrideSchedPolicy(RegionPolicy, Region);
// After subtarget overrides, apply command line options.
if (!EnableRegPressure) {
@@ -4332,7 +4314,6 @@ void PostGenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
MachineBasicBlock::iterator End,
unsigned NumRegionInstrs) {
const MachineFunction &MF = *Begin->getMF();
- const MachineBasicBlock &MBB = *Begin->getParent();
// Default to top-down because it was implemented first and existing targets
// expect that behavior by default.
@@ -4340,8 +4321,8 @@ void PostGenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
RegionPolicy.OnlyBottomUp = false;
// Allow the subtarget to override default policy.
- MF.getSubtarget().overridePostRASchedPolicy(RegionPolicy, MBB,
- NumRegionInstrs);
+ SchedRegion Region(Begin, End, NumRegionInstrs);
+ MF.getSubtarget().overridePostRASchedPolicy(RegionPolicy, Region);
// After subtarget overrides, apply command line options.
if (PostRADirection == MISched::TopDown) {
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
index 26dadebbe6302..0f4f0129e9cd3 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -534,8 +534,7 @@ unsigned AArch64Subtarget::classifyGlobalFunctionReference(
}
void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
- const MachineBasicBlock &MBB,
- unsigned NumRegionInstrs) const {
+ const SchedRegion &Region) const {
// LNT run (at least on Cyclone) showed reasonably significant gains for
// bi-directional scheduling. 253.perlbmk.
Policy.OnlyTopDown = false;
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index ce31de73160c4..061ed611e5e47 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -343,8 +343,8 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
}
void overrideSchedPolicy(MachineSchedPolicy &Policy,
- const MachineBasicBlock &MBB,
- unsigned NumRegionInstrs) const override;
+ const SchedRegion &Region) const override;
+
void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx,
SDep &Dep,
const TargetSchedModel *SchedModel) const override;
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
index 6b75da37f1d5f..9a2bab108232d 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
@@ -324,8 +324,7 @@ bool GCNSubtarget::zeroesHigh16BitsOfDest(unsigned Opcode) const {
}
void GCNSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
- const MachineBasicBlock &MBB,
- unsigned NumRegionInstrs) const {
+ const SchedRegion &Region) const {
// Track register pressure so the scheduler can try to decrease
// pressure once register usage is above the threshold defined by
// SIRegisterInfo::getRegPressureSetLimit()
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index 7b7efc4109d28..6e655019b4991 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -1020,8 +1020,7 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
}
void overrideSchedPolicy(MachineSchedPolicy &Policy,
- const MachineBasicBlock &MBB,
- unsigned NumRegionInstrs) const override;
+ const SchedRegion &Region) const override;
void mirFileLoaded(MachineFunction &MF) const override;
diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
index e5d7ce082c645..996b6efb320df 100644
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -171,8 +171,7 @@ void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
}
void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
- const MachineBasicBlock &MBB,
- unsigned NumRegionInstrs) const {
+ const SchedRegion &Region) const {
// The GenericScheduler that we use defaults to scheduling bottom up only.
// We want to schedule from both the top and the bottom and so we set
// OnlyBottomUp to false.
diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.h b/llvm/lib/Target/PowerPC/PPCSubtarget.h
index e45e17b3968b9..3c59a475c7eb6 100644
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -240,8 +240,8 @@ class PPCSubtarget : public PPCGenSubtargetInfo {
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
void overrideSchedPolicy(MachineSchedPolicy &Policy,
- const MachineBasicBlock &MBB,
- unsigned NumRegionInstrs) const override;
+ const SchedRegion &Region) const override;
+
bool useAA() const override;
bool enableSubRegLiveness() const override;
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index 2162445721df9..e35ffaf2b3935 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -216,8 +216,7 @@ unsigned RISCVSubtarget::getMinimumJumpTableEntries() const {
}
void RISCVSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
- const MachineBasicBlock &MBB,
- unsigned NumRegionInstrs) const {
+ const SchedRegion &Region) const {
// Do bidirectional scheduling since it provides a more balanced scheduling
// leading to better performance. This will increase compile time.
Policy.OnlyTopDown = false;
@@ -232,9 +231,8 @@ void RISCVSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
Policy.ShouldTrackPressure = true;
}
-void RISCVSubtarget::overridePostRASchedPolicy(MachineSchedPolicy &Policy,
- const MachineBasicBlock &MBB,
- unsigned NumRegionInstrs) const {
+void RISCVSubtarget::overridePostRASchedPolicy(
+ MachineSchedPolicy &Policy, const SchedRegion &Region) const {
MISched::Direction PostRASchedDirection = getPostRASchedDirection();
if (PostRASchedDirection == MISched::TopDown) {
Policy.OnlyTopDown = true;
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 325ae72b522ac..fd57e02c25d05 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -395,13 +395,11 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
}
void overrideSchedPolicy(MachineSchedPolicy &Policy,
- const MachineBasicBlock &MBB,
- unsigned NumRegionInstrs) const override;
+ const SchedRegion &Region) const override;
void overridePostRASchedPolicy(MachineSchedPolicy &Policy,
- const MachineBasicBlock &MBB,
- unsigned NumRegionInstrs) const override;
+ const SchedRegion &Region) const override;
};
-} // End llvm namespace
+} // namespace llvm
#endif
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