[llvm] [SelectionDAG] Pass SDNodeFlags through getNode instead of setFlags. (PR #149852)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 21 11:51:43 PDT 2025
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/149852
>From edaf7f23f4ac3332a9821bc5ad7c9708748a2963 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 21 Jul 2025 09:18:47 -0700
Subject: [PATCH] [SelectionDAG] Pass SDNodeFlags through getNode instead of
setFlags.
getNode updates flags correctly for CSE. Calling setFlags after
getNode may set the flags where they don't apply.
I've added flags to getSelectCC and the signature of getNode that
takes an ArrayRef of EVTs.
---
llvm/include/llvm/CodeGen/SelectionDAG.h | 10 ++--
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 7 +--
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 50 ++++++++-----------
.../SelectionDAG/LegalizeVectorOps.cpp | 9 ++--
.../SelectionDAG/LegalizeVectorTypes.cpp | 26 +++++-----
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 11 +++-
.../CodeGen/SelectionDAG/TargetLowering.cpp | 5 +-
7 files changed, 59 insertions(+), 59 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h
index 657951ddafd4f..30dd3bd0591f5 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -1202,13 +1202,16 @@ class SelectionDAG {
LLVM_ABI SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
ArrayRef<SDValue> Ops, const SDNodeFlags Flags);
LLVM_ABI SDValue getNode(unsigned Opcode, const SDLoc &DL,
- ArrayRef<EVT> ResultTys, ArrayRef<SDValue> Ops);
+ ArrayRef<EVT> ResultTys, ArrayRef<SDValue> Ops,
+ const SDNodeFlags Flags);
LLVM_ABI SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
ArrayRef<SDValue> Ops, const SDNodeFlags Flags);
// Use flags from current flag inserter.
LLVM_ABI SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
ArrayRef<SDValue> Ops);
+ LLVM_ABI SDValue getNode(unsigned Opcode, const SDLoc &DL,
+ ArrayRef<EVT> ResultTys, ArrayRef<SDValue> Ops);
LLVM_ABI SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
ArrayRef<SDValue> Ops);
LLVM_ABI SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
@@ -1346,9 +1349,10 @@ class SelectionDAG {
/// Helper function to make it easier to build SelectCC's if you just have an
/// ISD::CondCode instead of an SDValue.
SDValue getSelectCC(const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue True,
- SDValue False, ISD::CondCode Cond) {
+ SDValue False, ISD::CondCode Cond,
+ SDNodeFlags Flags = SDNodeFlags()) {
return getNode(ISD::SELECT_CC, DL, True.getValueType(), LHS, RHS, True,
- False, getCondCode(Cond));
+ False, getCondCode(Cond), Flags);
}
/// Try to simplify a select/vselect into 1 of its operands or a constant.
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index fed5e7238433e..f159746b24ff2 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -12375,11 +12375,8 @@ SDValue DAGCombiner::visitSELECT(SDNode *N) {
TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))) {
// Any flags available in a select/setcc fold will be on the setcc as they
// migrated from fcmp
- Flags = N0->getFlags();
- SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, VT, Cond0, Cond1, N1,
- N2, N0.getOperand(2));
- SelectNode->setFlags(Flags);
- return SelectNode;
+ return DAG.getNode(ISD::SELECT_CC, DL, VT, Cond0, Cond1, N1, N2,
+ N0.getOperand(2), N0->getFlags());
}
if (SDValue ABD = foldSelectToABD(Cond0, Cond1, N1, N2, CC, DL))
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 7266940c94bf1..74172b230361d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -2785,19 +2785,17 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(SDNode *Node,
// In strict mode, we must avoid spurious exceptions, and therefore
// must make sure to only emit a single STRICT_SINT_TO_FP.
SDValue InCvt = DAG.getSelect(dl, SrcVT, SignBitTest, Or, Op0);
- Fast = DAG.getNode(ISD::STRICT_SINT_TO_FP, dl, { DestVT, MVT::Other },
- { Node->getOperand(0), InCvt });
- Slow = DAG.getNode(ISD::STRICT_FADD, dl, { DestVT, MVT::Other },
- { Fast.getValue(1), Fast, Fast });
- Chain = Slow.getValue(1);
// The STRICT_SINT_TO_FP inherits the exception mode from the
// incoming STRICT_UINT_TO_FP node; the STRICT_FADD node can
// never raise any exception.
SDNodeFlags Flags;
Flags.setNoFPExcept(Node->getFlags().hasNoFPExcept());
- Fast->setFlags(Flags);
+ Fast = DAG.getNode(ISD::STRICT_SINT_TO_FP, dl, {DestVT, MVT::Other},
+ {Node->getOperand(0), InCvt}, Flags);
Flags.setNoFPExcept(true);
- Slow->setFlags(Flags);
+ Slow = DAG.getNode(ISD::STRICT_FADD, dl, {DestVT, MVT::Other},
+ {Fast.getValue(1), Fast, Fast}, Flags);
+ Chain = Slow.getValue(1);
} else {
SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Or);
Slow = DAG.getNode(ISD::FADD, dl, DestVT, SignCvt, SignCvt);
@@ -3407,14 +3405,12 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
EVT VT = Operand.getValueType();
SDValue One = DAG.getConstantFP(1.0, dl, VT);
SDValue Chain = DAG.getEntryNode();
- SDValue Mul = DAG.getNode(ISD::STRICT_FMUL, dl, {VT, MVT::Other},
- {Chain, Operand, One});
-
// Propagate existing flags on canonicalize, and additionally set
// NoFPExcept.
SDNodeFlags CanonicalizeFlags = Node->getFlags();
CanonicalizeFlags.setNoFPExcept(true);
- Mul->setFlags(CanonicalizeFlags);
+ SDValue Mul = DAG.getNode(ISD::STRICT_FMUL, dl, {VT, MVT::Other},
+ {Chain, Operand, One}, CanonicalizeFlags);
Results.push_back(Mul);
break;
@@ -4150,15 +4146,14 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
Tmp2 = Node->getOperand(1);
Tmp3 = Node->getOperand(2);
if (Tmp1.getOpcode() == ISD::SETCC) {
- Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
- Tmp2, Tmp3,
- cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
+ Tmp1 = DAG.getSelectCC(
+ dl, Tmp1.getOperand(0), Tmp1.getOperand(1), Tmp2, Tmp3,
+ cast<CondCodeSDNode>(Tmp1.getOperand(2))->get(), Node->getFlags());
} else {
- Tmp1 = DAG.getSelectCC(dl, Tmp1,
- DAG.getConstant(0, dl, Tmp1.getValueType()),
- Tmp2, Tmp3, ISD::SETNE);
+ Tmp1 =
+ DAG.getSelectCC(dl, Tmp1, DAG.getConstant(0, dl, Tmp1.getValueType()),
+ Tmp2, Tmp3, ISD::SETNE, Node->getFlags());
}
- Tmp1->setFlags(Node->getFlags());
Results.push_back(Tmp1);
break;
case ISD::BR_JT: {
@@ -4296,8 +4291,8 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
EVT Tmp1VT = Tmp1.getValueType();
Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
DAG.getBoolConstant(true, dl, VT, Tmp1VT),
- DAG.getBoolConstant(false, dl, VT, Tmp1VT), Tmp3);
- Tmp1->setFlags(Node->getFlags());
+ DAG.getBoolConstant(false, dl, VT, Tmp1VT), Tmp3,
+ Node->getFlags());
Results.push_back(Tmp1);
break;
}
@@ -4335,8 +4330,8 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
if (TLI.isCondCodeLegalOrCustom(InvCC, Tmp1.getSimpleValueType())) {
// Use the new condition code and swap true and false
Legalized = true;
- Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
- Tmp1->setFlags(Node->getFlags());
+ Tmp1 =
+ DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC, Node->getFlags());
} else {
// If The inverse is not legal, then try to swap the arguments using
// the inverse condition code.
@@ -4345,8 +4340,8 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
// The swapped inverse condition is legal, so swap true and false,
// lhs and rhs.
Legalized = true;
- Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
- Tmp1->setFlags(Node->getFlags());
+ Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC,
+ Node->getFlags());
}
}
@@ -4365,15 +4360,14 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
// If we expanded the SETCC by swapping LHS and RHS, or by inverting the
// condition code, create a new SELECT_CC node.
if (CC.getNode()) {
- Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
- Tmp1, Tmp2, Tmp3, Tmp4, CC);
+ Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
+ Tmp2, Tmp3, Tmp4, CC, Node->getFlags());
} else {
Tmp2 = DAG.getConstant(0, dl, Tmp1.getValueType());
CC = DAG.getCondCode(ISD::SETNE);
Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
- Tmp2, Tmp3, Tmp4, CC);
+ Tmp2, Tmp3, Tmp4, CC, Node->getFlags());
}
- Tmp1->setFlags(Node->getFlags());
}
Results.push_back(Tmp1);
break;
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index f908a66128ec8..d2ecc13331e02 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -2087,11 +2087,10 @@ void VectorLegalizer::ExpandSETCC(SDNode *Node,
// Otherwise, SETCC for the given comparison type must be completely
// illegal; expand it into a SELECT_CC.
EVT VT = Node->getValueType(0);
- LHS =
- DAG.getNode(ISD::SELECT_CC, dl, VT, LHS, RHS,
- DAG.getBoolConstant(true, dl, VT, LHS.getValueType()),
- DAG.getBoolConstant(false, dl, VT, LHS.getValueType()), CC);
- LHS->setFlags(Node->getFlags());
+ LHS = DAG.getNode(ISD::SELECT_CC, dl, VT, LHS, RHS,
+ DAG.getBoolConstant(true, dl, VT, LHS.getValueType()),
+ DAG.getBoolConstant(false, dl, VT, LHS.getValueType()),
+ CC, Node->getFlags());
}
Results.push_back(LHS);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 32c5961195450..1661814d5a897 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -372,9 +372,9 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_OverflowOp(SDNode *N,
SDVTList ScalarVTs = DAG.getVTList(
ResVT.getVectorElementType(), OvVT.getVectorElementType());
- SDNode *ScalarNode = DAG.getNode(
- N->getOpcode(), DL, ScalarVTs, ScalarLHS, ScalarRHS).getNode();
- ScalarNode->setFlags(N->getFlags());
+ SDNode *ScalarNode = DAG.getNode(N->getOpcode(), DL, ScalarVTs,
+ {ScalarLHS, ScalarRHS}, N->getFlags())
+ .getNode();
// Replace the other vector result not being explicitly scalarized here.
unsigned OtherNo = 1 - ResNo;
@@ -1898,7 +1898,7 @@ SDValue DAGTypeLegalizer::UnrollVectorOp_StrictFP(SDNode *N, unsigned ResNE) {
NE = ResNE;
//The results of each unrolled operation, including the chain.
- EVT ChainVTs[] = {EltVT, MVT::Other};
+ SDVTList ChainVTs = DAG.getVTList(EltVT, MVT::Other);
SmallVector<SDValue, 8> Chains;
unsigned i;
@@ -1914,8 +1914,8 @@ SDValue DAGTypeLegalizer::UnrollVectorOp_StrictFP(SDNode *N, unsigned ResNE) {
Operands[j] = Operand;
}
}
- SDValue Scalar = DAG.getNode(N->getOpcode(), dl, ChainVTs, Operands);
- Scalar.getNode()->setFlags(N->getFlags());
+ SDValue Scalar =
+ DAG.getNode(N->getOpcode(), dl, ChainVTs, Operands, N->getFlags());
//Add in the scalar as well as its chain value to the
//result vectors.
@@ -1956,10 +1956,10 @@ void DAGTypeLegalizer::SplitVecRes_OverflowOp(SDNode *N, unsigned ResNo,
unsigned Opcode = N->getOpcode();
SDVTList LoVTs = DAG.getVTList(LoResVT, LoOvVT);
SDVTList HiVTs = DAG.getVTList(HiResVT, HiOvVT);
- SDNode *LoNode = DAG.getNode(Opcode, dl, LoVTs, LoLHS, LoRHS).getNode();
- SDNode *HiNode = DAG.getNode(Opcode, dl, HiVTs, HiLHS, HiRHS).getNode();
- LoNode->setFlags(N->getFlags());
- HiNode->setFlags(N->getFlags());
+ SDNode *LoNode =
+ DAG.getNode(Opcode, dl, LoVTs, {LoLHS, LoRHS}, N->getFlags()).getNode();
+ SDNode *HiNode =
+ DAG.getNode(Opcode, dl, HiVTs, {HiLHS, HiRHS}, N->getFlags()).getNode();
Lo = SDValue(LoNode, ResNo);
Hi = SDValue(HiNode, ResNo);
@@ -2669,10 +2669,8 @@ void DAGTypeLegalizer::SplitVecRes_UnaryOpWithTwoResults(SDNode *N,
else
std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
- Lo = DAG.getNode(N->getOpcode(), dl, {LoVT, LoVT1}, Lo);
- Hi = DAG.getNode(N->getOpcode(), dl, {HiVT, HiVT1}, Hi);
- Lo->setFlags(N->getFlags());
- Hi->setFlags(N->getFlags());
+ Lo = DAG.getNode(N->getOpcode(), dl, {LoVT, LoVT1}, Lo, N->getFlags());
+ Hi = DAG.getNode(N->getOpcode(), dl, {HiVT, HiVT1}, Hi, N->getFlags());
SDNode *HiNode = Hi.getNode();
SDNode *LoNode = Lo.getNode();
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 245811587e3b4..76680b2afc7a1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -10699,7 +10699,16 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL,
ArrayRef<EVT> ResultTys, ArrayRef<SDValue> Ops) {
- return getNode(Opcode, DL, getVTList(ResultTys), Ops);
+ SDNodeFlags Flags;
+ if (Inserter)
+ Flags = Inserter->getFlags();
+ return getNode(Opcode, DL, getVTList(ResultTys), Ops, Flags);
+}
+
+SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL,
+ ArrayRef<EVT> ResultTys, ArrayRef<SDValue> Ops,
+ const SDNodeFlags Flags) {
+ return getNode(Opcode, DL, getVTList(ResultTys), Ops, Flags);
}
SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 37fddcf943681..a578d1c24abc5 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -8634,9 +8634,8 @@ TargetLowering::createSelectForFMINNUM_FMAXNUM(SDNode *Node,
return SDValue();
SDValue Op1 = Node->getOperand(0);
SDValue Op2 = Node->getOperand(1);
- SDValue SelCC = DAG.getSelectCC(SDLoc(Node), Op1, Op2, Op1, Op2, Pred);
- SelCC->setFlags(Node->getFlags());
- return SelCC;
+ return DAG.getSelectCC(SDLoc(Node), Op1, Op2, Op1, Op2, Pred,
+ Node->getFlags());
}
return SDValue();
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