[llvm] [RISCV] Separate the analysis part of RISCVInsertVSETVLI. (PR #149574)

[Min-Yih Hsu via llvm-commits]

mshockwave wrote:

> @topperc @preames @mshockwave Which part of this has to have virtual registers?

I forgot the context and only remember you wanted to reuse the analysis after (both) RA? But in general, InsertVSETVLI Pass expects all scalar register to be virtual, as it's preceded by RVV RA and followed by scalar RA. 

https://github.com/llvm/llvm-project/pull/149574