[llvm] [AArch64][CodeGen] Optimize register zero initialization in svsub_x (PR #149840)

[David Green via llvm-commits]

davemgreen wrote:

> There is a difference in how registers are zeroed in GCC and LLVM.

They both do the same thing and clear the entire register. You can see the "Zero Latency MOVs" section of the SWOG for the instructions that are more efficiently executed, AFAUI they are both on there so should perform the same.

The aarch64_sve_sub_u combine could be in instcombine via AArch64TTIImpl::instCombineIntrinsic, unless you think it will only appear duing lowering? The fsub version too but that requires nnan.

https://github.com/llvm/llvm-project/pull/149840