[llvm] [RISCV][RFC] Add additional opcodes to RISCVDAGToDAGISel::hasAllNBitUsers (PR #147728)
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 21 06:45:36 PDT 2025
https://github.com/asb updated https://github.com/llvm/llvm-project/pull/147728
>From cd7e155f5e826869a4e98a9b60dfc0eaa668097d Mon Sep 17 00:00:00 2001
From: Alex Bradbury <asb at igalia.com>
Date: Wed, 9 Jul 2025 14:38:33 +0100
Subject: [PATCH 1/4] [RISCV] Add additional opcodes to
RISCVDAGToDAGISel::hasAllNBitUsers
This adds opcodes that are handled in the RISCVOptWInstrs version but
not the SDag version.
---
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 31 +++++++++++++++++++--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 4539efd591c8b..b097fb9b414ea 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3606,11 +3606,15 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits,
if (Use.getOperandNo() == 1 && Bits >= Log2_32(Subtarget->getXLen()))
break;
return false;
- case RISCV::SLLI:
+ case RISCV::SLLI: {
// SLLI only uses the lower (XLen - ShAmt) bits.
- if (Bits >= Subtarget->getXLen() - User->getConstantOperandVal(1))
+ uint64_t ShAmt = User->getConstantOperandVal(1);
+ if (Bits >= Subtarget->getXLen() - ShAmt)
+ break;
+ if (hasAllNBitUsers(User, Bits + ShAmt, Depth + 1))
break;
return false;
+ }
case RISCV::ANDI:
if (Bits >= (unsigned)llvm::bit_width(User->getConstantOperandVal(1)))
break;
@@ -3621,20 +3625,39 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits,
break;
[[fallthrough]];
}
+ case RISCV::COPY:
+ case RISCV::PHI:
+ case RISCV::ADD:
+ case RISCV::ADDI:
case RISCV::AND:
+ case RISCV::MUL:
case RISCV::OR:
+ case RISCV::SUB:
case RISCV::XOR:
case RISCV::XORI:
case RISCV::ANDN:
+ case RISCV::BREV8:
+ case RISCV::CLMUL:
+ case RISCV::ORC_B:
case RISCV::ORN:
case RISCV::XNOR:
case RISCV::SH1ADD:
case RISCV::SH2ADD:
case RISCV::SH3ADD:
+ case RISCV::BSETI:
+ case RISCV::BCLRI:
+ case RISCV::BINVI:
RecCheck:
if (hasAllNBitUsers(User, Bits, Depth + 1))
break;
return false;
+ case RISCV::CZERO_EQZ:
+ case RISCV::CZERO_NEZ:
+ if (Use.getOperandNo() != 0)
+ return false;
+ if (hasAllNBitUsers(User, Bits, Depth + 1))
+ break;
+ return false;
case RISCV::SRLI: {
unsigned ShAmt = User->getConstantOperandVal(1);
// If we are shifting right by less than Bits, and users don't demand any
@@ -3670,6 +3693,10 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits,
if (Use.getOperandNo() == 0 && Bits >= 32)
break;
return false;
+ case RISCV::BEXTI:
+ if (User->getConstantOperandVal(1) >= Bits)
+ return false;
+ break;
case RISCV::SB:
if (Use.getOperandNo() == 0 && Bits >= 8)
break;
>From 61c1b22116e639314ecfcdf0d66f460f2eb3029c Mon Sep 17 00:00:00 2001
From: Alex Bradbury <asb at igalia.com>
Date: Mon, 21 Jul 2025 14:41:12 +0100
Subject: [PATCH 2/4] Incorporate corrected ORC_B/BREV8 logic from #148076
---
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 9cf8cbcf5901b..cb70f7280ee8c 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3768,9 +3768,7 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits,
case RISCV::XOR:
case RISCV::XORI:
case RISCV::ANDN:
- case RISCV::BREV8:
case RISCV::CLMUL:
- case RISCV::ORC_B:
case RISCV::ORN:
case RISCV::XNOR:
case RISCV::SH1ADD:
@@ -3783,6 +3781,11 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits,
if (hasAllNBitUsers(User, Bits, Depth + 1))
break;
return false;
+ case RISCV::BREV8:
+ case RISCV::ORC_B:
+ if (hasAllNBitUsers(User, alignDown(Bits, 8), Depth + 1))
+ break;
+ return false;
case RISCV::CZERO_EQZ:
case RISCV::CZERO_NEZ:
if (Use.getOperandNo() != 0)
>From bbd1a88a4d4b621f2045ae26a9375df058f22806 Mon Sep 17 00:00:00 2001
From: Alex Bradbury <asb at igalia.com>
Date: Mon, 21 Jul 2025 14:42:53 +0100
Subject: [PATCH 3/4] Correct comment
---
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index cb70f7280ee8c..6c47c42b68535 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3734,7 +3734,7 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits,
case RISCV::BSET:
case RISCV::BCLR:
case RISCV::BINV:
- // Shift amount operands only use log2(Xlen) bits.
+ // Shift amount / bit index operands only use log2(Xlen) bits.
if (Use.getOperandNo() == 1 && Bits >= Log2_32(Subtarget->getXLen()))
break;
return false;
>From 9c6283897b9e5bb67fb94c190be56e256a38e4d8 Mon Sep 17 00:00:00 2001
From: Alex Bradbury <asb at igalia.com>
Date: Mon, 21 Jul 2025 14:45:06 +0100
Subject: [PATCH 4/4] Adopt SLLIW hasAllNBitUsers improvement from #148344
---
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 6c47c42b68535..e0aa5772e4c64 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3692,7 +3692,6 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits,
case RISCV::SUBW:
case RISCV::MULW:
case RISCV::SLLW:
- case RISCV::SLLIW:
case RISCV::SRAW:
case RISCV::SRAIW:
case RISCV::SRLW:
@@ -3747,6 +3746,14 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits,
break;
return false;
}
+ case RISCV::SLLIW: {
+ uint64_t ShAmt = User->getConstantOperandVal(1);
+ if (Bits >= 32 - ShAmt)
+ break;
+ if (hasAllNBitUsers(User, Bits + ShAmt, Depth + 1))
+ break;
+ return false;
+ }
case RISCV::ANDI:
if (Bits >= (unsigned)llvm::bit_width(User->getConstantOperandVal(1)))
break;
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