[llvm] [AMDGPU][SDAG] Handle ISD::PTRADD in VOP3 patterns (PR #143881)

[Fabian Ritter via llvm-commits]

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@@ -908,19 +919,24 @@ multiclass IMAD32_Pats <VOP3_Pseudo inst> {
 
 // Handle cases where amdgpu-codegenprepare-mul24 made a mul24 instead of a normal mul.
 // We need to separate this because otherwise OtherPredicates would be overriden.
-class IMAD32_Mul24_Pat<VOP3_Pseudo inst>: GCNPat <
-    (i64 (add (i64 (AMDGPUmul_u24 i32:$src0, i32:$src1)), i64:$src2)),
-    (inst $src0, $src1, $src2, 0 /* clamp */)
-    >;
+class IMAD32_Mul24_Pats_Impl<VOP3_Pseudo inst, SDPatternOperator AddOp, bit mulIsRight = 0> : GCNPat <
+    !if(mulIsRight, (i64 (AddOp i64:$src2, (i64 (AMDGPUmul_u24 i32:$src0, i32:$src1)))),
+                    (i64 (AddOp (i64 (AMDGPUmul_u24 i32:$src0, i32:$src1)), i64:$src2))),
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ritter-x2a wrote:

@arsenm, what do you think of this way to make `ptradd` commutable in some DAG patterns?

Alternatively, I could add a field to the `Pattern` tablegen class, similarly to `GISelShouldIgnore`, that is queried in `CodeGenDAGPatterns`' `GenerateVariants`, for example:
- a single `bit PtrAddCommutative` that is hardcoded to mean that `ptradd` should be treated as commutative in this pattern or
- a less hard-coded `list<SDPatternOperator> ForceOperatorCommutative` that gets a list of operators that should be treated as commutative in this pattern.

As far as I can see, that would however just add more complexity in the tablegen backend to achieve the same goal as the current or the previous implementation in this PR.

https://github.com/llvm/llvm-project/pull/143881