[llvm] [RISC-V] Update SpacemiT-X60 Vector Integer latencies (PR #149207)
Mikhail R. Gadelha via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 18 13:22:58 PDT 2025
================
@@ -322,71 +403,120 @@ foreach LMul = [1, 2, 4, 8] in {
foreach mx = SchedMxList in {
defvar IsWorstCase = SMX60IsWorstCaseMX<mx, SchedMxList>.c;
- defm "" : LMULWriteResMX<"WriteVIALUV", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIALUX", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIALUI", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVExtV", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVICALUV", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVICALUX", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVICALUI", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVICALUMV", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVICALUMX", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVICALUMI", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVICmpV", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVICmpX", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVICmpI", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIMinMaxV", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIMinMaxX", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIMergeV", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIMergeX", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIMergeI", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIMovV", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIMovX", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIMovI", [SMX60_VIEU], mx, IsWorstCase>;
-
- defm "" : LMULWriteResMX<"WriteVShiftV", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVShiftX", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVShiftI", [SMX60_VIEU], mx, IsWorstCase>;
-
- defm "" : LMULWriteResMX<"WriteVIMulV", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIMulX", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIMulAddV", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIMulAddX", [SMX60_VIEU], mx, IsWorstCase>;
+ let Latency = Get4458Latency<mx>.c, ReleaseAtCycles = [Get1248Latency<mx>.c] in {
+ defm "" : LMULWriteResMX<"WriteVIMinMaxV", [SMX60_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMinMaxX", [SMX60_VIEU], mx, IsWorstCase>;
+ }
+
+ let Latency = Get44816Latency<mx>.c, ReleaseAtCycles = [Get44816Latency<mx>.c] in {
+ // Pattern of vadd, vsub, vrsub: 4/4/5/8
+ // Pattern of vand, vor, vxor: 4/4/8/16
+ // They are grouped together, so we used the worst case 4/4/5/16
+ // TODO: use InstRW to override individual instructions' scheduling data
+ defm "" : LMULWriteResMX<"WriteVIALUV", [SMX60_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIALUX", [SMX60_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIALUI", [SMX60_VIEU], mx, IsWorstCase>;
+
+ defm "" : LMULWriteResMX<"WriteVExtV", [SMX60_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMergeV", [SMX60_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMergeX", [SMX60_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMergeI", [SMX60_VIEU], mx, IsWorstCase>;
----------------
mikhailramalho wrote:
Do you mean the Latency or the ReleaseAtCycles?
The measured latencies are:
| Instruction | e8mf8 | e8mf4 | e8mf2 | e8m1 | e8m2 | e8m4 | e8m8 | e16mf4 | e16mf2 | e16m1 | e16m2 | e16m4 | e16m8 | e32mf2 | e32m1 | e32m2 | e32m4 | e32m8 | e64mf2 | e64m1 | e64m2 | e64m4 | e64m8 |
|--------------|-------|-------|-------|------|------|------|------|---------|---------|--------|--------|--------|--------|---------|--------|--------|--------|--------|---------|--------|--------|--------|--------|
| vand.vi | 4 | 4 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 8 | 16 |
| vand.vv | 4 | 4 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 8 | 16 |
| vand.vx | 4 | 4 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 8 | 16 |
| vor.vi | 4 | 4 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 8 | 16 |
| vor.vv | 4 | 4 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 8 | 16 |
| vor.vx | 4 | 4 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 8 | 16 |
| vxor.vi | 4 | 4 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 8 | 16 |
| vxor.vv | 4 | 4 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 8 | 16 |
| vxor.vx | 4 | 4 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 8 | 16 |
| vmerge.vim | 4 | 4 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 8 | 16 |
| vmerge.vvm | 4 | 4 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 8 | 16 |
| vmerge.vxm | 4 | 4 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 4 | 8 | 16 | 4 | 4 | 8 | 16 |
https://github.com/llvm/llvm-project/pull/149207
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