[llvm] [AMDGPU] Recognise bitmask operations as srcmods (PR #149110)

[Chris Jackson via llvm-commits]

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@@ -3036,6 +3036,41 @@ bool AMDGPUDAGToDAGISel::SelectVOP3ModsImpl(SDValue In, SDValue &Src,
     Src = Src.getOperand(0);
   }
 
+  // Convert various sign-bit masks to src mods. Currently disabled for 16-bit
+  // types as the codegen replaces the operand without adding a srcmod.
+  // This is intentionally finding the cases where we are performing float neg
+  // and abs on int types, the goal is not to obtain two's complement neg or
+  // abs.
+  // TODO: Add 16-bit support.
+  unsigned Opc = Src->getOpcode();
+  EVT VT = Src.getValueType();
+  if ((Opc != ISD::AND && Opc != ISD::OR && Opc != ISD::XOR) ||
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chrisjbris wrote:

I believe the instructions do, but here we're checking the inputs to IR instructions that will be lowered to VOP3 instructions, not VOP3 instructions themselves. (As far as I understand it here).

As an experiment I removed any check for operand(1) existing and many lit tests failed.

https://github.com/llvm/llvm-project/pull/149110