[llvm] [llvm] Support multiple save/restore points in mir (PR #119357)

[Matt Arsenault via llvm-commits]

================
@@ -651,6 +679,67 @@ static void insertCSRRestores(MachineBasicBlock &RestoreBlock,
   }
 }
 
+static void fillCSInfoPerBB(MachineFrameInfo &MFI,
+                            DenseMap<Register, CalleeSavedInfo *> &RegToInfo,
+                            MBBVector &PrologEpilogBlocks, bool isSave) {
+  // Global CalleeSavedInfo list aggregating CSIVs for all points
+  std::vector<CalleeSavedInfo> GCSIV;
+  const SaveRestorePoints::PointsMap &SRPoints =
+      isSave ? MFI.getSavePoints() : MFI.getRestorePoints();
+  SaveRestorePoints::PointsMap Inner;
+  for (auto [BB, Regs] : SRPoints) {
+    // CalleeSavedInfo list for each point
+    std::vector<CalleeSavedInfo> CSIV;
+    for (auto &Reg : Regs) {
+      auto It = RegToInfo.find(Reg.getReg());
+      if (It == RegToInfo.end())
+        continue;
+      CSIV.push_back(*RegToInfo.at(Reg.getReg()));
+      GCSIV.push_back(*RegToInfo.at(Reg.getReg()));
+    }
+    // We need to sort CSIV, because Aarch64 expect CSI list to come sorted by
+    // frame index
+    std::sort(CSIV.begin(), CSIV.end(),
+              [](const CalleeSavedInfo &Lhs, const CalleeSavedInfo &Rhs) {
+                return Lhs.getFrameIdx() < Rhs.getFrameIdx();
+              });
+    Inner.try_emplace(BB, std::move(CSIV));
+  }
+
+  // If in any case not all CSRs listed in MFI.getCalleeSavedInfo are in the
+  // list of spilled/restored registers (for example AArch64 backend add VG
+  // registers in the list of CalleeSavedRegs during spill slot assignment), we
+  // should add them to this list and spill/restore them in Prolog/Epilog.
+  if (GCSIV.size() < RegToInfo.size()) {
+    for (auto &RTI : RegToInfo) {
+      if (find_if(GCSIV, [&RTI](const CalleeSavedInfo &CSI) {
+            return CSI.getReg() == RTI.first;
+          }) != std::end(GCSIV))
----------------
arsenm wrote:

```suggestion
      if (is_contained(GCSIV, [&RTI](const CalleeSavedInfo &CSI) {
            return CSI.getReg() == RTI.first;
          }))
```

https://github.com/llvm/llvm-project/pull/119357