[llvm] [AArch64] Allow splitting bitmasks for ANDS. (PR #149095)

[David Green via llvm-commits]

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@@ -263,3 +263,110 @@ entry:
   %conv = zext i1 %cmp to i8
   ret i8 %conv
 }
+
+; Test ANDS.
+define i32 @test1_ands(i32 %a) {
+; CHECK-LABEL: test1_ands:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    and w8, w0, #0x3ffc00
+; CHECK-NEXT:    ands w8, w8, #0xffe007ff
+; CHECK-NEXT:    csel w0, w8, wzr, eq
+; CHECK-NEXT:    ret
+entry:
+  %ands = and i32 %a, 2098176
+  %c = icmp eq i32 %ands, 0
+  %r = select i1 %c, i32 %ands, i32 0
+  ret i32 %r
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davemgreen wrote:

I think this is just 0 because picks `ands == 0 ? ands : 0`. Can we change it to something that would not optimize away?

https://github.com/llvm/llvm-project/pull/149095