[llvm] [MISched] Extend overridePostRASchedPolicy to support per-function scheduling direction (PR #149297)
Harrison Hao via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 18 00:21:10 PDT 2025
https://github.com/harrisonGPU updated https://github.com/llvm/llvm-project/pull/149297
>From e9d38f6a352f6fd59e72fa4ee90fdb280798b4fe Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Thu, 17 Jul 2025 20:06:28 +0800
Subject: [PATCH 1/2] [MISched] Extend overridePostRASchedPolicy to support
per-function scheduling direction
---
llvm/include/llvm/CodeGen/TargetSubtargetInfo.h | 2 +-
llvm/lib/CodeGen/MachineScheduler.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVSubtarget.cpp | 4 ++--
llvm/lib/Target/RISCV/RISCVSubtarget.h | 4 ++--
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
index 45e67d80629cb..0e6162aed9df8 100644
--- a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
@@ -241,7 +241,7 @@ class LLVM_ABI TargetSubtargetInfo : public MCSubtargetInfo {
/// Note that some options like tracking register pressure won't take effect
/// in post-ra scheduling.
virtual void overridePostRASchedPolicy(MachineSchedPolicy &Policy,
- unsigned NumRegionInstrs) const {}
+ const MachineFunction &MF) const {}
// Perform target-specific adjustments to the latency of a schedule
// dependency.
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 76cba2949af60..dfea60a84ad45 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -4338,7 +4338,7 @@ void PostGenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
RegionPolicy.OnlyBottomUp = false;
// Allow the subtarget to override default policy.
- MF.getSubtarget().overridePostRASchedPolicy(RegionPolicy, NumRegionInstrs);
+ MF.getSubtarget().overridePostRASchedPolicy(RegionPolicy, MF);
// After subtarget overrides, apply command line options.
if (PostRADirection == MISched::TopDown) {
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index c754de45db7fd..628d82b16b7fe 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -231,8 +231,8 @@ void RISCVSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
Policy.ShouldTrackPressure = true;
}
-void RISCVSubtarget::overridePostRASchedPolicy(MachineSchedPolicy &Policy,
- unsigned NumRegionInstrs) const {
+void RISCVSubtarget::overridePostRASchedPolicy(
+ MachineSchedPolicy &Policy, const MachineFunction &MF) const {
MISched::Direction PostRASchedDirection = getPostRASchedDirection();
if (PostRASchedDirection == MISched::TopDown) {
Policy.OnlyTopDown = true;
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 4f560cca22dff..55f44ac9da1d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -398,8 +398,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
unsigned NumRegionInstrs) const override;
void overridePostRASchedPolicy(MachineSchedPolicy &Policy,
- unsigned NumRegionInstrs) const override;
+ const MachineFunction &MF) const override;
};
-} // End llvm namespace
+} // namespace llvm
#endif
>From cf2392fd967f887e869d6e5ca4e0fa00aa378e27 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Fri, 18 Jul 2025 14:32:54 +0800
Subject: [PATCH 2/2] [MISched] Add MachineBasicBlock.
---
llvm/include/llvm/CodeGen/MachineScheduler.h | 1 +
llvm/include/llvm/CodeGen/TargetSubtargetInfo.h | 5 ++++-
llvm/lib/CodeGen/MachineScheduler.cpp | 7 +++++--
llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 1 +
llvm/lib/Target/AArch64/AArch64Subtarget.h | 1 +
llvm/lib/Target/AMDGPU/GCNSubtarget.cpp | 1 +
llvm/lib/Target/AMDGPU/GCNSubtarget.h | 5 ++---
llvm/lib/Target/PowerPC/PPCSubtarget.cpp | 5 +++--
llvm/lib/Target/PowerPC/PPCSubtarget.h | 1 +
llvm/lib/Target/RISCV/RISCVSubtarget.cpp | 6 ++++--
llvm/lib/Target/RISCV/RISCVSubtarget.h | 4 +++-
11 files changed, 26 insertions(+), 11 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h
index e7a7091acee64..1d37874acd72b 100644
--- a/llvm/include/llvm/CodeGen/MachineScheduler.h
+++ b/llvm/include/llvm/CodeGen/MachineScheduler.h
@@ -65,6 +65,7 @@
//
// void <SubTarget>Subtarget::
// overrideSchedPolicy(MachineSchedPolicy &Policy,
+// const MachineBasicBlock &MBB,
// unsigned NumRegionInstrs) const {
// Policy.<Flag> = true;
// }
diff --git a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
index 0e6162aed9df8..014e7ccaa004c 100644
--- a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
@@ -16,6 +16,7 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MacroFusion.h"
#include "llvm/CodeGen/PBQPRAConstraint.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
@@ -231,6 +232,7 @@ class LLVM_ABI TargetSubtargetInfo : public MCSubtargetInfo {
/// scheduling heuristics (no custom MachineSchedStrategy) to make
/// changes to the generic scheduling policy.
virtual void overrideSchedPolicy(MachineSchedPolicy &Policy,
+ const MachineBasicBlock &MBB,
unsigned NumRegionInstrs) const {}
/// Override generic post-ra scheduling policy within a region.
@@ -241,7 +243,8 @@ class LLVM_ABI TargetSubtargetInfo : public MCSubtargetInfo {
/// Note that some options like tracking register pressure won't take effect
/// in post-ra scheduling.
virtual void overridePostRASchedPolicy(MachineSchedPolicy &Policy,
- const MachineFunction &MF) const {}
+ const MachineBasicBlock &MBB,
+ unsigned NumRegionInstrs) const {}
// Perform target-specific adjustments to the latency of a schedule
// dependency.
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index dfea60a84ad45..80c238417d727 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -3703,6 +3703,7 @@ void GenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
MachineBasicBlock::iterator End,
unsigned NumRegionInstrs) {
const MachineFunction &MF = *Begin->getMF();
+ const MachineBasicBlock &MBB = *Begin->getParent();
const TargetLowering *TLI = MF.getSubtarget().getTargetLowering();
// Avoid setting up the register pressure tracker for small regions to save
@@ -3725,7 +3726,7 @@ void GenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
RegionPolicy.OnlyBottomUp = true;
// Allow the subtarget to override default policy.
- MF.getSubtarget().overrideSchedPolicy(RegionPolicy, NumRegionInstrs);
+ MF.getSubtarget().overrideSchedPolicy(RegionPolicy, MBB, NumRegionInstrs);
// After subtarget overrides, apply command line options.
if (!EnableRegPressure) {
@@ -4331,6 +4332,7 @@ void PostGenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
MachineBasicBlock::iterator End,
unsigned NumRegionInstrs) {
const MachineFunction &MF = *Begin->getMF();
+ const MachineBasicBlock &MBB = *Begin->getParent();
// Default to top-down because it was implemented first and existing targets
// expect that behavior by default.
@@ -4338,7 +4340,8 @@ void PostGenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
RegionPolicy.OnlyBottomUp = false;
// Allow the subtarget to override default policy.
- MF.getSubtarget().overridePostRASchedPolicy(RegionPolicy, MF);
+ MF.getSubtarget().overridePostRASchedPolicy(RegionPolicy, MBB,
+ NumRegionInstrs);
// After subtarget overrides, apply command line options.
if (PostRADirection == MISched::TopDown) {
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
index 2409cc862f21c..26dadebbe6302 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -534,6 +534,7 @@ unsigned AArch64Subtarget::classifyGlobalFunctionReference(
}
void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
+ const MachineBasicBlock &MBB,
unsigned NumRegionInstrs) const {
// LNT run (at least on Cyclone) showed reasonably significant gains for
// bi-directional scheduling. 253.perlbmk.
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index 154db3c074f71..ce31de73160c4 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -343,6 +343,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
}
void overrideSchedPolicy(MachineSchedPolicy &Policy,
+ const MachineBasicBlock &MBB,
unsigned NumRegionInstrs) const override;
void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx,
SDep &Dep,
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
index 7b8f0f44cbe2c..6b75da37f1d5f 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
@@ -324,6 +324,7 @@ bool GCNSubtarget::zeroesHigh16BitsOfDest(unsigned Opcode) const {
}
void GCNSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
+ const MachineBasicBlock &MBB,
unsigned NumRegionInstrs) const {
// Track register pressure so the scheduler can try to decrease
// pressure once register usage is above the threshold defined by
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index 68430526dba26..5265ae70d8378 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -1015,11 +1015,10 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
static bool hasHalfRate64Ops(const TargetSubtargetInfo &STI);
// XXX - Why is this here if it isn't in the default pass set?
- bool enableEarlyIfConversion() const override {
- return true;
- }
+ bool enableEarlyIfConversion() const override { return true; }
void overrideSchedPolicy(MachineSchedPolicy &Policy,
+ const MachineBasicBlock &MBB,
unsigned NumRegionInstrs) const override;
void mirFileLoaded(MachineFunction &MF) const override;
diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
index 75a0272af7c31..0d88495de3550 100644
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -166,11 +166,12 @@ PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const
void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
CriticalPathRCs.clear();
- CriticalPathRCs.push_back(isPPC64() ?
- &PPC::G8RCRegClass : &PPC::GPRCRegClass);
+ CriticalPathRCs.push_back(isPPC64() ? &PPC::G8RCRegClass
+ : &PPC::GPRCRegClass);
}
void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
+ const MachineBasicBlock &MBB,
unsigned NumRegionInstrs) const {
// The GenericScheduler that we use defaults to scheduling bottom up only.
// We want to schedule from both the top and the bottom and so we set
diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.h b/llvm/lib/Target/PowerPC/PPCSubtarget.h
index 9a97d1aa4dab0..e45e17b3968b9 100644
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -240,6 +240,7 @@ class PPCSubtarget : public PPCGenSubtargetInfo {
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
void overrideSchedPolicy(MachineSchedPolicy &Policy,
+ const MachineBasicBlock &MBB,
unsigned NumRegionInstrs) const override;
bool useAA() const override;
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index 628d82b16b7fe..2162445721df9 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -216,6 +216,7 @@ unsigned RISCVSubtarget::getMinimumJumpTableEntries() const {
}
void RISCVSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
+ const MachineBasicBlock &MBB,
unsigned NumRegionInstrs) const {
// Do bidirectional scheduling since it provides a more balanced scheduling
// leading to better performance. This will increase compile time.
@@ -231,8 +232,9 @@ void RISCVSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
Policy.ShouldTrackPressure = true;
}
-void RISCVSubtarget::overridePostRASchedPolicy(
- MachineSchedPolicy &Policy, const MachineFunction &MF) const {
+void RISCVSubtarget::overridePostRASchedPolicy(MachineSchedPolicy &Policy,
+ const MachineBasicBlock &MBB,
+ unsigned NumRegionInstrs) const {
MISched::Direction PostRASchedDirection = getPostRASchedDirection();
if (PostRASchedDirection == MISched::TopDown) {
Policy.OnlyTopDown = true;
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 55f44ac9da1d1..fffc7e3ef23df 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -395,10 +395,12 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
}
void overrideSchedPolicy(MachineSchedPolicy &Policy,
+ const MachineBasicBlock &MBB,
unsigned NumRegionInstrs) const override;
void overridePostRASchedPolicy(MachineSchedPolicy &Policy,
- const MachineFunction &MF) const override;
+ const MachineBasicBlock &MBB,
+ unsigned NumRegionInstrs) const override;
};
} // namespace llvm
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