[llvm] Adding abdu/abds to canCreateUndefOrPoison (PR #149017)
Annu Singh via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 17 23:20:28 PDT 2025
https://github.com/AnnuCode updated https://github.com/llvm/llvm-project/pull/149017
>From c2bd312fe9e40770477683df42db3d13ddd848a3 Mon Sep 17 00:00:00 2001
From: Annu Singh <annu4444.as at gmail.com>
Date: Wed, 16 Jul 2025 04:22:38 +0000
Subject: [PATCH 1/2] abdu/abds to canCreateUndefOrPoison
---
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 2 +
llvm/test/CodeGen/AArch64/freeze.ll | 48 +++++++++++++++++++
2 files changed, 50 insertions(+)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 70a39eab1e720..11028cae2e43a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5619,6 +5619,8 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
case ISD::ADD:
case ISD::SUB:
case ISD::MUL:
+ case ISD::ABDU:
+ case ISD::ABDS:
case ISD::FNEG:
case ISD::FADD:
case ISD::FSUB:
diff --git a/llvm/test/CodeGen/AArch64/freeze.ll b/llvm/test/CodeGen/AArch64/freeze.ll
index 0c56e1b66e81f..63ee03e36efb2 100644
--- a/llvm/test/CodeGen/AArch64/freeze.ll
+++ b/llvm/test/CodeGen/AArch64/freeze.ll
@@ -395,3 +395,51 @@ define i64 @freeze_array() {
%t1 = add i64 %v1, %v2
ret i64 %t1
}
+
+define i32 @freeze_abdu(i8 %x, i8 %y) {
+; CHECK-SD-LABEL: freeze_abdu:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: and w8, w0, #0xff
+; CHECK-SD-NEXT: sub w8, w8, w1, uxtb
+; CHECK-SD-NEXT: cmp w8, #0
+; CHECK-SD-NEXT: cneg w0, w8, mi
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: freeze_abdu:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: and w8, w0, #0xff
+; CHECK-GI-NEXT: sub w8, w8, w1, uxtb
+; CHECK-GI-NEXT: cmp w8, #0
+; CHECK-GI-NEXT: cneg w0, w8, le
+; CHECK-GI-NEXT: ret
+ %a = zext i8 %x to i32
+ %b = zext i8 %y to i32
+ %d = sub i32 %a, %b
+ %t = call i32 @llvm.abs.i32(i32 %d, i1 false)
+ %f = freeze i32 %t
+ ret i32 %f
+}
+
+define i32 @freeze_abds(i8 %x, i8 %y) {
+; CHECK-SD-LABEL: freeze_abds:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sxtb w8, w0
+; CHECK-SD-NEXT: sub w8, w8, w1, sxtb
+; CHECK-SD-NEXT: cmp w8, #0
+; CHECK-SD-NEXT: cneg w0, w8, mi
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: freeze_abds:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sxtb w8, w0
+; CHECK-GI-NEXT: sub w8, w8, w1, sxtb
+; CHECK-GI-NEXT: cmp w8, #0
+; CHECK-GI-NEXT: cneg w0, w8, le
+; CHECK-GI-NEXT: ret
+ %a = sext i8 %x to i32
+ %b = sext i8 %y to i32
+ %d = sub i32 %a, %b
+ %abs = call i32 @llvm.abs.i32(i32 %d, i1 true)
+ %f = freeze i32 %abs
+ ret i32 %f
+}
>From 20cfaeb8c7704e575599dc6a2929d097d50b761d Mon Sep 17 00:00:00 2001
From: Annu Singh <annu4444.as at gmail.com>
Date: Fri, 18 Jul 2025 06:16:12 +0000
Subject: [PATCH 2/2] updating tests
---
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 4 +-
llvm/test/CodeGen/AArch64/freeze.ll | 46 +++++++------------
2 files changed, 18 insertions(+), 32 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 11028cae2e43a..f7143ed24f5a8 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5544,6 +5544,8 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
case ISD::USUBSAT:
case ISD::MULHU:
case ISD::MULHS:
+ case ISD::ABDU:
+ case ISD::ABDS:
case ISD::SMIN:
case ISD::SMAX:
case ISD::UMIN:
@@ -5619,8 +5621,6 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
case ISD::ADD:
case ISD::SUB:
case ISD::MUL:
- case ISD::ABDU:
- case ISD::ABDS:
case ISD::FNEG:
case ISD::FADD:
case ISD::FSUB:
diff --git a/llvm/test/CodeGen/AArch64/freeze.ll b/llvm/test/CodeGen/AArch64/freeze.ll
index 63ee03e36efb2..d428b6aa483a7 100644
--- a/llvm/test/CodeGen/AArch64/freeze.ll
+++ b/llvm/test/CodeGen/AArch64/freeze.ll
@@ -396,50 +396,36 @@ define i64 @freeze_array() {
ret i64 %t1
}
-define i32 @freeze_abdu(i8 %x, i8 %y) {
+define <8 x i16> @freeze_abdu(<8 x i16> %a, <8 x i16> %b) {
; CHECK-SD-LABEL: freeze_abdu:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: and w8, w0, #0xff
-; CHECK-SD-NEXT: sub w8, w8, w1, uxtb
-; CHECK-SD-NEXT: cmp w8, #0
-; CHECK-SD-NEXT: cneg w0, w8, mi
+; CHECK-SD-NEXT: uaba v0.8h, v0.8h, v1.8h
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: freeze_abdu:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: and w8, w0, #0xff
-; CHECK-GI-NEXT: sub w8, w8, w1, uxtb
-; CHECK-GI-NEXT: cmp w8, #0
-; CHECK-GI-NEXT: cneg w0, w8, le
+; CHECK-GI-NEXT: uabd v1.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: add v0.8h, v0.8h, v1.8h
; CHECK-GI-NEXT: ret
- %a = zext i8 %x to i32
- %b = zext i8 %y to i32
- %d = sub i32 %a, %b
- %t = call i32 @llvm.abs.i32(i32 %d, i1 false)
- %f = freeze i32 %t
- ret i32 %f
+ %d = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> %a, <8 x i16> %b)
+ %f = freeze <8 x i16> %d
+ %r = add <8 x i16> %a, %f
+ ret <8 x i16> %r
}
-define i32 @freeze_abds(i8 %x, i8 %y) {
+define <8 x i16> @freeze_abds(<8 x i16> %a, <8 x i16> %b) {
; CHECK-SD-LABEL: freeze_abds:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: sxtb w8, w0
-; CHECK-SD-NEXT: sub w8, w8, w1, sxtb
-; CHECK-SD-NEXT: cmp w8, #0
-; CHECK-SD-NEXT: cneg w0, w8, mi
+; CHECK-SD-NEXT: saba v0.8h, v0.8h, v1.8h
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: freeze_abds:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sxtb w8, w0
-; CHECK-GI-NEXT: sub w8, w8, w1, sxtb
-; CHECK-GI-NEXT: cmp w8, #0
-; CHECK-GI-NEXT: cneg w0, w8, le
+; CHECK-GI-NEXT: sabd v1.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: add v0.8h, v0.8h, v1.8h
; CHECK-GI-NEXT: ret
- %a = sext i8 %x to i32
- %b = sext i8 %y to i32
- %d = sub i32 %a, %b
- %abs = call i32 @llvm.abs.i32(i32 %d, i1 true)
- %f = freeze i32 %abs
- ret i32 %f
+ %d = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> %a, <8 x i16> %b)
+ %f = freeze <8 x i16> %d
+ %r = add <8 x i16> %a, %f
+ ret <8 x i16> %r
}
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