[llvm] [AArch64] Keep floating-point conversion in SIMD (PR #147707)

[Guy David via llvm-commits]

guy-david wrote:

> > > > > Is it possible to write this as a post legalisation DAG combine? to remove the need for dedicated isel patterns.
> > > > 
> > > > 
> > > > Do you mean a pattern that combines stores whenever the source is a `fp_to_sint`, or the other way around?
> > > 
> > > 
> > > I was thinking the former. There's already a combine to handle the case where the source is `ISD::EXTRACT_VECTOR_ELT` and was wondering if you could convert the scalar `fp_to_sint` to a vector one and then the existing combine would then convert the store to floating point. This might be easier said than done as we've tripped over this before for the SME streaming mode case but I'm hoping that logic can be reused here.
> > 
> > 
> > Sounds feasible, although I don't have too much experience with that. Can we postpone it to a follow-up PR?
> 
> I'd rather not postpone, but am happy to take a look to see what's involved.

I've hit a few blockers around legalization, see 147d2c683e104d914b28592c7239f77d44a10e6a:
- `v1i32 fp_to_sint v1f32` is legalized to `v2i32 fp_to_sint v2f32`, couldn't figure out how to prevent this.
- `v1i64 fp_to_sint v1f64` fails more miserably and hits `"Unable to legalize as libcall"`.

https://github.com/llvm/llvm-project/pull/147707