[llvm] [MISched] Extend overridePostRASchedPolicy to support per-function scheduling direction (PR #149297)

[Harrison Hao via llvm-commits]

https://github.com/harrisonGPU created https://github.com/llvm/llvm-project/pull/149297

The current `overridePostRASchedPolicy` method receives `NumRegionInstrs`,
but this value is not actually useful when determining post-RA scheduling direction.

To support setting the direction via a function attribute, we replace the unused
argument with `MachineFunction`, allowing access to per-function metadata.

For example:
```cpp
void overridePostRASchedPolicy(MachineSchedPolicy &Policy,
const MachineFunction &MF) const {
    const Function &F = MF.getFunction();
    Attribute Attr = F.getFnAttribute("function-attribute");
...
}
```
This avoids the need to encode scheduling direction in target features and enables
finer-grained, per-shader control over post-RA scheduling.

>From e9d38f6a352f6fd59e72fa4ee90fdb280798b4fe Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Thu, 17 Jul 2025 20:06:28 +0800
Subject: [PATCH] [MISched] Extend overridePostRASchedPolicy to support
 per-function scheduling direction

---
 llvm/include/llvm/CodeGen/TargetSubtargetInfo.h | 2 +-
 llvm/lib/CodeGen/MachineScheduler.cpp           | 2 +-
 llvm/lib/Target/RISCV/RISCVSubtarget.cpp        | 4 ++--
 llvm/lib/Target/RISCV/RISCVSubtarget.h          | 4 ++--
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
index 45e67d80629cb..0e6162aed9df8 100644
--- a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
@@ -241,7 +241,7 @@ class LLVM_ABI TargetSubtargetInfo : public MCSubtargetInfo {
   /// Note that some options like tracking register pressure won't take effect
   /// in post-ra scheduling.
   virtual void overridePostRASchedPolicy(MachineSchedPolicy &Policy,
-                                         unsigned NumRegionInstrs) const {}
+                                         const MachineFunction &MF) const {}
 
   // Perform target-specific adjustments to the latency of a schedule
   // dependency.
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 76cba2949af60..dfea60a84ad45 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -4338,7 +4338,7 @@ void PostGenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
   RegionPolicy.OnlyBottomUp = false;
 
   // Allow the subtarget to override default policy.
-  MF.getSubtarget().overridePostRASchedPolicy(RegionPolicy, NumRegionInstrs);
+  MF.getSubtarget().overridePostRASchedPolicy(RegionPolicy, MF);
 
   // After subtarget overrides, apply command line options.
   if (PostRADirection == MISched::TopDown) {
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index c754de45db7fd..628d82b16b7fe 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -231,8 +231,8 @@ void RISCVSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
   Policy.ShouldTrackPressure = true;
 }
 
-void RISCVSubtarget::overridePostRASchedPolicy(MachineSchedPolicy &Policy,
-                                               unsigned NumRegionInstrs) const {
+void RISCVSubtarget::overridePostRASchedPolicy(
+    MachineSchedPolicy &Policy, const MachineFunction &MF) const {
   MISched::Direction PostRASchedDirection = getPostRASchedDirection();
   if (PostRASchedDirection == MISched::TopDown) {
     Policy.OnlyTopDown = true;
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 4f560cca22dff..55f44ac9da1d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -398,8 +398,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
                            unsigned NumRegionInstrs) const override;
 
   void overridePostRASchedPolicy(MachineSchedPolicy &Policy,
-                                 unsigned NumRegionInstrs) const override;
+                                 const MachineFunction &MF) const override;
 };
-} // End llvm namespace
+} // namespace llvm
 
 #endif