[llvm] [RISCV] Teach SelectAddrRegRegScale that ADD is commutable. (PR #149231)

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:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp -- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index e05b92759..3fc493fb6 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3036,7 +3036,8 @@ static bool isWorthFoldingSHLOverADDI(SDValue Addi, SDValue Shift,
                                       const RISCVSubtarget &Subtarget) {
   unsigned ShiftAmt = Shift.getConstantOperandVal(1);
 
-  if (ShiftAmt <= 3 && (Subtarget.hasStdExtZba() || Subtarget.hasVendorXTHeadBa()))
+  if (ShiftAmt <= 3 &&
+      (Subtarget.hasStdExtZba() || Subtarget.hasVendorXTHeadBa()))
     return false;
 
   if (ShiftAmt >= 4 && Subtarget.hasVendorXqciac())

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https://github.com/llvm/llvm-project/pull/149231