[llvm] [AArch64] Allow splitting bitmasks for ANDS, EOR and ORR. (PR #149095)

[Ricardo Jesus via llvm-commits]

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@@ -263,3 +263,282 @@ entry:
   %conv = zext i1 %cmp to i8
   ret i8 %conv
 }
+
+; Test ANDS.
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rj-jesus wrote:

The new tests are based on the simple preexisting AND tests.

https://github.com/llvm/llvm-project/pull/149095