[llvm] [DemandedBits] Add div/rem support (PR #148853)

[Nikita Popov via llvm-commits]

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@@ -246,6 +246,31 @@ void DemandedBits::determineLiveOperandBits(
     else
       AB &= ~(Known.One & ~Known2.One);
     break;
+  case Instruction::SRem:
+  case Instruction::URem:
+  case Instruction::UDiv:
+  case Instruction::SDiv: {
+    auto Opc = UserI->getOpcode();
+    auto IsDiv = Opc == Instruction::UDiv || Opc == Instruction::SDiv;
+    bool IsSigned = Opc == Instruction::SDiv || Opc == Instruction::SRem;
+    if (OperandNo == 0) {
+      const APInt *DivAmnt;
+      if (match(UserI->getOperand(1), m_APInt(DivAmnt))) {
+        if (DivAmnt->isPowerOf2()) {
+          unsigned Sh = DivAmnt->countr_zero();
+          if (IsDiv) {
+            AB = AOut.shl(Sh);
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nikic wrote:

This is not correct for signed division. Simple example:

(-1 s/ 2) & 1 is 0.
(-1&2 s/ 2) & 1 is 1.

https://github.com/llvm/llvm-project/pull/148853