[llvm] [PowerPC] Add intrinsic definition for load and store with Right Length Left-justified (PR #148873)
Lei Huang via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 15 10:53:12 PDT 2025
https://github.com/lei137 updated https://github.com/llvm/llvm-project/pull/148873
>From a7af8791f627d5a0e3c5d5017bf9bad9fec9d0b0 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Fri, 11 Jul 2025 20:10:23 +0000
Subject: [PATCH 1/6] add intrinsic def for ld/st with Right Length
Left-justified
---
llvm/include/llvm/IR/IntrinsicsPowerPC.td | 25 ++++++++++++++++
llvm/lib/Target/PowerPC/PPCInstrFuture.td | 9 ++++++
.../CodeGen/PowerPC/vsx-ldst-with-length.ll | 29 +++++++++++++++++++
3 files changed, 63 insertions(+)
create mode 100644 llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index 7dd9ff7f08b8b..33c6b3011dc67 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1351,6 +1351,18 @@ def int_ppc_vsx_lxvll :
def int_ppc_vsx_lxvp :
DefaultAttrsIntrinsic<[llvm_v256i1_ty], [llvm_ptr_ty],
[IntrReadMem, IntrArgMemOnly]>;
+def int_ppc_vsx_lxvrl :
+ DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_ptr_ty, llvm_i64_ty],
+ [IntrReadMem, IntrArgMemOnly]>;
+def int_ppc_vsx_lxvrll :
+ DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_ptr_ty, llvm_i64_ty],
+ [IntrReadMem, IntrArgMemOnly]>;
+def int_ppc_vsx_lxvprl :
+ DefaultAttrsIntrinsic<[llvm_v256i1_ty], [llvm_ptr_ty, llvm_i64_ty],
+ [IntrReadMem, IntrArgMemOnly]>;
+def int_ppc_vsx_lxvprll :
+ DefaultAttrsIntrinsic<[llvm_v256i1_ty], [llvm_ptr_ty, llvm_i64_ty],
+ [IntrReadMem, IntrArgMemOnly]>;
// Vector store.
def int_ppc_vsx_stxvw4x : Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty],
@@ -1370,6 +1382,19 @@ def int_ppc_vsx_stxvll :
def int_ppc_vsx_stxvp :
Intrinsic<[], [llvm_v256i1_ty, llvm_ptr_ty], [IntrWriteMem,
IntrArgMemOnly]>;
+def int_ppc_vsx_stxvrl :
+ Intrinsic<[], [llvm_anyvector_ty, llvm_ptr_ty, llvm_i64_ty],
+ [IntrWriteMem, IntrArgMemOnly]>;
+def int_ppc_vsx_stxvrll :
+ Intrinsic<[], [llvm_anyvector_ty, llvm_ptr_ty, llvm_i64_ty],
+ [IntrWriteMem, IntrArgMemOnly]>;
+def int_ppc_vsx_stxvprl :
+ Intrinsic<[], [llvm_v256i1_ty, llvm_ptr_ty, llvm_i64_ty], [IntrWriteMem,
+ IntrArgMemOnly]>;
+def int_ppc_vsx_stxvprll :
+ Intrinsic<[], [llvm_v256i1_ty, llvm_ptr_ty, llvm_i64_ty], [IntrWriteMem,
+ IntrArgMemOnly]>;
+
// Vector and scalar maximum.
def int_ppc_vsx_xvmaxdp : PowerPC_VSX_Vec_DDD_Intrinsic<"xvmaxdp">;
def int_ppc_vsx_xvmaxsp : PowerPC_VSX_Vec_FFF_Intrinsic<"xvmaxsp">;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index 1ac91fadf6582..cd879aae17191 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -86,3 +86,12 @@ let Predicates = [HasVSX, IsISAFuture] in {
"stxvprll $XTp, $RA, $RB", IIC_LdStLFD, []>;
}
}
+
+def : Pat<(v4i32 (int_ppc_vsx_lxvrl addr:$RA, i64:$RB)), (LXVRL $RA, $RB)>;
+def : Pat<(v4i32 (int_ppc_vsx_lxvrll addr:$RA, i64:$RB)), (LXVRLL $RA, $RB)>;
+def : Pat<(v256i1 (int_ppc_vsx_lxvprl addr:$RA, i64:$RB)), (LXVPRL $RA, $RB)>;
+def : Pat<(v256i1 (int_ppc_vsx_lxvprll addr:$RA, i64:$RB)), (LXVPRLL $RA, $RB)>;
+/*
+def : Pat<(int_ppc_vsx_stxvrl v256i1:$XT, addr:$RA, i64:$RB),
+ (STXVRL $XT, $RA, $RB)>;
+*/
diff --git a/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
new file mode 100644
index 0000000000000..d55e27697804f
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=future < %s | \
+; RUN: FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \
+; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=future < %s | \
+; RUN: FileCheck %s
+
+define <4 x i32> @testLXVRL(ptr %a, i64 %b) {
+; CHECK-LABEL: testLXVRL:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lxvrl v2, r3, r4
+; CHECK-NEXT: blr
+entry:
+ %0 = tail call <4 x i32> @llvm.ppc.vsx.lxvrl(ptr %a, i64 %b)
+ ret <4 x i32> %0
+}
+declare <4 x i32> @llvm.ppc.vsx.lxvrl(ptr, i64)
+
+define <4 x i32> @testLXVRLL(ptr %a, i64 %b) {
+; CHECK-LABEL: testLXVRLL:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lxvrll v2, r3, r4
+; CHECK-NEXT: blr
+entry:
+ %0 = tail call <4 x i32> @llvm.ppc.vsx.lxvrll(ptr %a, i64 %b)
+ ret <4 x i32> %0
+}
+declare <4 x i32> @llvm.ppc.vsx.lxvrll(ptr, i64)
>From 5ee36ceffa9d697d4355f1f8024a1e22665c7a1f Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Fri, 11 Jul 2025 20:38:19 +0000
Subject: [PATCH 2/6] add ld tests
---
.../CodeGen/PowerPC/vsx-ldst-with-length.ll | 23 +++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
index d55e27697804f..aa32be404960b 100644
--- a/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
+++ b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
@@ -27,3 +27,26 @@ entry:
ret <4 x i32> %0
}
declare <4 x i32> @llvm.ppc.vsx.lxvrll(ptr, i64)
+
+define <256 x i1> @testLXVPRL(ptr %vpp, i64 %b) {
+; CHECK-LABEL: testLXVPRL:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lxvprl vsp34, r4, r5
+; CHECK: blr
+entry:
+ %0 = tail call <256 x i1> @llvm.ppc.vsx.lxvprl(ptr %vpp, i64 %b)
+ ret <256 x i1> %0
+}
+declare <256 x i1> @llvm.ppc.vsx.lxvprl(ptr, i64)
+
+define <256 x i1> @testLXVPRLL(ptr %vpp, i64 %b) {
+; CHECK-LABEL: testLXVPRLL:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lxvprll vsp34, r4, r5
+; CHECK: blr
+entry:
+ %0 = tail call <256 x i1> @llvm.ppc.vsx.lxvprll(ptr %vpp, i64 %b)
+ ret <256 x i1> %0
+}
+declare <256 x i1> @llvm.ppc.vsx.lxvprll(ptr, i64)
+
>From 736a783b77fed637cd537a35b2bdf642e790bcf0 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Fri, 11 Jul 2025 21:22:29 +0000
Subject: [PATCH 3/6] add stxvprl[l]
---
llvm/lib/Target/PowerPC/PPCInstrFuture.td | 13 ++++++++---
.../CodeGen/PowerPC/vsx-ldst-with-length.ll | 22 ++++++++++++++++++-
2 files changed, 31 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index cd879aae17191..6edc854294418 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -87,11 +87,18 @@ let Predicates = [HasVSX, IsISAFuture] in {
}
}
+// Load VSX Vector with Right Length Left-justified.
def : Pat<(v4i32 (int_ppc_vsx_lxvrl addr:$RA, i64:$RB)), (LXVRL $RA, $RB)>;
def : Pat<(v4i32 (int_ppc_vsx_lxvrll addr:$RA, i64:$RB)), (LXVRLL $RA, $RB)>;
def : Pat<(v256i1 (int_ppc_vsx_lxvprl addr:$RA, i64:$RB)), (LXVPRL $RA, $RB)>;
def : Pat<(v256i1 (int_ppc_vsx_lxvprll addr:$RA, i64:$RB)), (LXVPRLL $RA, $RB)>;
-/*
-def : Pat<(int_ppc_vsx_stxvrl v256i1:$XT, addr:$RA, i64:$RB),
+
+// Store VSX Vector with Right Length Left-justified.
+def : Pat<(int_ppc_vsx_stxvrl v4i32:$XT, addr:$RA, i64:$RB),
(STXVRL $XT, $RA, $RB)>;
-*/
+def : Pat<(int_ppc_vsx_stxvrll v4i32:$XT, addr:$RA, i64:$RB),
+ (STXVRLL $XT, $RA, $RB)>;
+def : Pat<(int_ppc_vsx_stxvprl v256i1:$XT, addr:$RA, i64:$RB),
+ (STXVPRL $XT, $RA, $RB)>;
+def : Pat<(int_ppc_vsx_stxvprll v256i1:$XT, addr:$RA, i64:$RB),
+ (STXVPRLL $XT, $RA, $RB)>;
diff --git a/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
index aa32be404960b..0fc9508fb9b10 100644
--- a/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
+++ b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=future < %s | \
; RUN: FileCheck %s
@@ -50,3 +49,24 @@ entry:
}
declare <256 x i1> @llvm.ppc.vsx.lxvprll(ptr, i64)
+define void @testSTXVRL(<4 x i32> %a, ptr %b, i64 %c) {
+; CHECK-LABEL: testSTXVRL:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: stxvrl v2, [[REG:r[0-9]+]], [[REG1:r[0-9]+]]
+; CHECK: blr
+entry:
+ tail call void @llvm.ppc.vsx.stxvrl(<4 x i32> %a, ptr %b, i64 %c)
+ ret void
+}
+declare void @llvm.ppc.vsx.stxvrl(<4 x i32>, ptr, i64)
+
+define void @testSTXVRLL(<4 x i32> %a, ptr %b, i64 %c) {
+; CHECK-LABEL: testSTXVRLL:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: stxvrll v2, [[REG:r[0-9]+]], [[REG1:r[0-9]+]]
+; CHECK: blr
+entry:
+ tail call void @llvm.ppc.vsx.stxvrll(<4 x i32> %a, ptr %b, i64 %c)
+ ret void
+}
+declare void @llvm.ppc.vsx.stxvrll(<4 x i32>, ptr, i64)
>From a8a1c22fd7210a275adea0fb89f580a0838c693f Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Fri, 11 Jul 2025 21:39:25 +0000
Subject: [PATCH 4/6] add stxvprl[l]
---
llvm/lib/Target/PowerPC/PPCInstrFuture.td | 8 +++---
.../CodeGen/PowerPC/vsx-ldst-with-length.ll | 28 +++++++++++++++++++
2 files changed, 32 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index 6edc854294418..420d6c3cfd72b 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -98,7 +98,7 @@ def : Pat<(int_ppc_vsx_stxvrl v4i32:$XT, addr:$RA, i64:$RB),
(STXVRL $XT, $RA, $RB)>;
def : Pat<(int_ppc_vsx_stxvrll v4i32:$XT, addr:$RA, i64:$RB),
(STXVRLL $XT, $RA, $RB)>;
-def : Pat<(int_ppc_vsx_stxvprl v256i1:$XT, addr:$RA, i64:$RB),
- (STXVPRL $XT, $RA, $RB)>;
-def : Pat<(int_ppc_vsx_stxvprll v256i1:$XT, addr:$RA, i64:$RB),
- (STXVPRLL $XT, $RA, $RB)>;
+def : Pat<(int_ppc_vsx_stxvprl v256i1:$XTp, addr:$RA, i64:$RB),
+ (STXVPRL $XTp, $RA, $RB)>;
+def : Pat<(int_ppc_vsx_stxvprll v256i1:$XTp, addr:$RA, i64:$RB),
+ (STXVPRLL $XTp, $RA, $RB)>;
diff --git a/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
index 0fc9508fb9b10..c1bbf64e5b09b 100644
--- a/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
+++ b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
@@ -70,3 +70,31 @@ entry:
ret void
}
declare void @llvm.ppc.vsx.stxvrll(<4 x i32>, ptr, i64)
+
+define void @testSTXVPRL(ptr %v, ptr %vp, i64 %len) {
+; CHECK-LABEL: testSTXVPRL:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lxv v2
+; CHECK-NEXT: lxv v3
+; CHECK-NEXT: stxvprl vsp34, r4, r5
+; CHECK-NEXT: blr
+entry:
+ %0 = load <256 x i1>, ptr %v, align 32
+ tail call void @llvm.ppc.vsx.stxvprl(<256 x i1> %0, ptr %vp, i64 %len)
+ ret void
+}
+declare void @llvm.ppc.vsx.stxvprl(<256 x i1>, ptr, i64)
+
+define void @testSTXVPRLL(ptr %v, ptr %vp, i64 %len) {
+; CHECK-LABEL: testSTXVPRLL:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lxv v2
+; CHECK-NEXT: lxv v3
+; CHECK-NEXT: stxvprll vsp34, r4, r5
+; CHECK-NEXT: blr
+entry:
+ %0 = load <256 x i1>, ptr %v, align 32
+ tail call void @llvm.ppc.vsx.stxvprll(<256 x i1> %0, ptr %vp, i64 %len)
+ ret void
+}
+declare void @llvm.ppc.vsx.stxvprll(<256 x i1>, ptr, i64)
>From 0239fb3b6fdff21e5b807e2fa2d9cab2e0afec71 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Tue, 15 Jul 2025 15:40:59 +0000
Subject: [PATCH 5/6] add support and test for v2i64
---
llvm/lib/Target/PowerPC/PPCInstrFuture.td | 65 +++++++-------
.../CodeGen/PowerPC/vsx-ldst-with-length.ll | 90 ++++++++++++++-----
2 files changed, 103 insertions(+), 52 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index 420d6c3cfd72b..7c7627795420c 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -53,51 +53,52 @@ let Predicates = [IsISAFuture] in {
let Predicates = [HasVSX, IsISAFuture] in {
let mayLoad = 1 in {
- def LXVRL : XX1Form_memOp<31, 525, (outs vsrc:$XT), (ins memr:$RA, g8rc:$RB),
- "lxvrl $XT, $RA, $RB", IIC_LdStLoad, []>;
-
- def LXVRLL : XX1Form_memOp<31, 557, (outs vsrc:$XT), (ins memr:$RA, g8rc:$RB),
- "lxvrll $XT, $RA, $RB", IIC_LdStLoad, []>;
-
- def LXVPRL : XForm_XTp5_XAB5<31, 589, (outs vsrprc:$XTp),
- (ins memr:$RA, g8rc:$RB),
- "lxvprl $XTp, $RA, $RB", IIC_LdStLFD, []>;
-
- def LXVPRLL : XForm_XTp5_XAB5<31, 621, (outs vsrprc:$XTp),
- (ins memr:$RA, g8rc:$RB),
- "lxvprll $XTp, $RA, $RB", IIC_LdStLFD, []>;
+ def LXVRL
+ : XX1Form_memOp<31, 525, (outs vsrc:$XT), (ins memr:$RA, g8rc:$RB),
+ "lxvrl $XT, $RA, $RB", IIC_LdStLoad, []>;
+ def LXVRLL
+ : XX1Form_memOp<31, 557, (outs vsrc:$XT), (ins memr:$RA, g8rc:$RB),
+ "lxvrll $XT, $RA, $RB", IIC_LdStLoad, []>;
+ def LXVPRL
+ : XForm_XTp5_XAB5<31, 589, (outs vsrprc:$XTp), (ins memr:$RA, g8rc:$RB),
+ "lxvprl $XTp, $RA, $RB", IIC_LdStLFD, []>;
+ def LXVPRLL
+ : XForm_XTp5_XAB5<31, 621, (outs vsrprc:$XTp), (ins memr:$RA, g8rc:$RB),
+ "lxvprll $XTp, $RA, $RB", IIC_LdStLFD, []>;
}
let mayStore = 1 in {
- def STXVRL : XX1Form_memOp<31, 653, (outs),
- (ins vsrc:$XT, memr:$RA, g8rc:$RB),
- "stxvrl $XT, $RA, $RB", IIC_LdStLoad, []>;
-
- def STXVRLL : XX1Form_memOp<31, 685, (outs),
- (ins vsrc:$XT, memr:$RA, g8rc:$RB),
- "stxvrll $XT, $RA, $RB", IIC_LdStLoad, []>;
-
+ def STXVRL
+ : XX1Form_memOp<31, 653, (outs), (ins vsrc:$XT, memr:$RA, g8rc:$RB),
+ "stxvrl $XT, $RA, $RB", IIC_LdStLoad, []>;
+ def STXVRLL
+ : XX1Form_memOp<31, 685, (outs), (ins vsrc:$XT, memr:$RA, g8rc:$RB),
+ "stxvrll $XT, $RA, $RB", IIC_LdStLoad, []>;
def STXVPRL : XForm_XTp5_XAB5<31, 717, (outs),
(ins vsrprc:$XTp, memr:$RA, g8rc:$RB),
"stxvprl $XTp, $RA, $RB", IIC_LdStLFD, []>;
-
def STXVPRLL : XForm_XTp5_XAB5<31, 749, (outs),
(ins vsrprc:$XTp, memr:$RA, g8rc:$RB),
"stxvprll $XTp, $RA, $RB", IIC_LdStLFD, []>;
}
}
-// Load VSX Vector with Right Length Left-justified.
-def : Pat<(v4i32 (int_ppc_vsx_lxvrl addr:$RA, i64:$RB)), (LXVRL $RA, $RB)>;
-def : Pat<(v4i32 (int_ppc_vsx_lxvrll addr:$RA, i64:$RB)), (LXVRLL $RA, $RB)>;
-def : Pat<(v256i1 (int_ppc_vsx_lxvprl addr:$RA, i64:$RB)), (LXVPRL $RA, $RB)>;
-def : Pat<(v256i1 (int_ppc_vsx_lxvprll addr:$RA, i64:$RB)), (LXVPRLL $RA, $RB)>;
+// Load/Store VSX Vector with Right Length Left-justified.
+// foreach Ty = [v4i32, v2i64, v128i1] in {
+foreach Ty = [v4i32, v2i64] in {
+ def : Pat<(Ty (int_ppc_vsx_lxvrl addr:$RA, i64:$RB)),
+ (LXVRL memr:$RA, g8rc:$RB)>;
+ def : Pat<(Ty (int_ppc_vsx_lxvrll addr:$RA, i64:$RB)),
+ (LXVRLL $RA, $RB)>;
+ def : Pat<(int_ppc_vsx_stxvrl Ty:$XT, addr:$RA, i64:$RB),
+ (STXVRL $XT, $RA, $RB)>;
+ def : Pat<(int_ppc_vsx_stxvrll Ty:$XT, addr:$RA, i64:$RB),
+ (STXVRLL $XT, $RA, $RB)>;
+}
-// Store VSX Vector with Right Length Left-justified.
-def : Pat<(int_ppc_vsx_stxvrl v4i32:$XT, addr:$RA, i64:$RB),
- (STXVRL $XT, $RA, $RB)>;
-def : Pat<(int_ppc_vsx_stxvrll v4i32:$XT, addr:$RA, i64:$RB),
- (STXVRLL $XT, $RA, $RB)>;
+// Load/Store VSX Vector pair with Right Length Left-justified.
+def : Pat<(v256i1(int_ppc_vsx_lxvprl addr:$RA, i64:$RB)), (LXVPRL $RA, $RB)>;
+def : Pat<(v256i1(int_ppc_vsx_lxvprll addr:$RA, i64:$RB)), (LXVPRLL $RA, $RB)>;
def : Pat<(int_ppc_vsx_stxvprl v256i1:$XTp, addr:$RA, i64:$RB),
(STXVPRL $XTp, $RA, $RB)>;
def : Pat<(int_ppc_vsx_stxvprll v256i1:$XTp, addr:$RA, i64:$RB),
diff --git a/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
index c1bbf64e5b09b..2cbaf3c548d28 100644
--- a/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
+++ b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
@@ -5,6 +5,8 @@
; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=future < %s | \
; RUN: FileCheck %s
+; Test for load/store to/from v4i32.
+
define <4 x i32> @testLXVRL(ptr %a, i64 %b) {
; CHECK-LABEL: testLXVRL:
; CHECK: # %bb.0: # %entry
@@ -27,49 +29,97 @@ entry:
}
declare <4 x i32> @llvm.ppc.vsx.lxvrll(ptr, i64)
-define <256 x i1> @testLXVPRL(ptr %vpp, i64 %b) {
-; CHECK-LABEL: testLXVPRL:
+define void @testSTXVRL(<4 x i32> %a, ptr %b, i64 %c) {
+; CHECK-LABEL: testSTXVRL:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxvprl vsp34, r4, r5
+; CHECK-NEXT: stxvrl v2, [[REG:r[0-9]+]], [[REG1:r[0-9]+]]
; CHECK: blr
entry:
- %0 = tail call <256 x i1> @llvm.ppc.vsx.lxvprl(ptr %vpp, i64 %b)
- ret <256 x i1> %0
+ tail call void @llvm.ppc.vsx.stxvrl(<4 x i32> %a, ptr %b, i64 %c)
+ ret void
}
-declare <256 x i1> @llvm.ppc.vsx.lxvprl(ptr, i64)
+declare void @llvm.ppc.vsx.stxvrl(<4 x i32>, ptr, i64)
-define <256 x i1> @testLXVPRLL(ptr %vpp, i64 %b) {
-; CHECK-LABEL: testLXVPRLL:
+define void @testSTXVRLL(<4 x i32> %a, ptr %b, i64 %c) {
+; CHECK-LABEL: testSTXVRLL:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxvprll vsp34, r4, r5
+; CHECK-NEXT: stxvrll v2, [[REG:r[0-9]+]], [[REG1:r[0-9]+]]
; CHECK: blr
entry:
- %0 = tail call <256 x i1> @llvm.ppc.vsx.lxvprll(ptr %vpp, i64 %b)
- ret <256 x i1> %0
+ tail call void @llvm.ppc.vsx.stxvrll(<4 x i32> %a, ptr %b, i64 %c)
+ ret void
}
-declare <256 x i1> @llvm.ppc.vsx.lxvprll(ptr, i64)
+declare void @llvm.ppc.vsx.stxvrll(<4 x i32>, ptr, i64)
-define void @testSTXVRL(<4 x i32> %a, ptr %b, i64 %c) {
-; CHECK-LABEL: testSTXVRL:
+; Test for load/store to/from v2i64.
+
+define <2 x i64> @testLXVRL2(ptr %a, i64 %b) {
+; CHECK-LABEL: testLXVRL2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lxvrl v2, r3, r4
+; CHECK-NEXT: blr
+entry:
+ %0 = tail call <2 x i64> @llvm.ppc.vsx.lxvrl.v2i64(ptr %a, i64 %b)
+ ret <2 x i64> %0
+}
+declare <2 x i64> @llvm.ppc.vsx.lxvrl.v2i64(ptr, i64)
+
+define <2 x i64> @testLXVRLL2(ptr %a, i64 %b) {
+; CHECK-LABEL: testLXVRLL2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lxvrll v2, r3, r4
+; CHECK-NEXT: blr
+entry:
+ %0 = tail call <2 x i64> @llvm.ppc.vsx.lxvrll.v2i64(ptr %a, i64 %b)
+ ret <2 x i64> %0
+}
+declare <2 x i64> @llvm.ppc.vsx.lxvrll.v2i64(ptr, i64)
+
+define void @testSTXVRL2(<2 x i64> %a, ptr %b, i64 %c) {
+; CHECK-LABEL: testSTXVRL2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stxvrl v2, [[REG:r[0-9]+]], [[REG1:r[0-9]+]]
; CHECK: blr
entry:
- tail call void @llvm.ppc.vsx.stxvrl(<4 x i32> %a, ptr %b, i64 %c)
+ tail call void @llvm.ppc.vsx.stxvrl.v2i64(<2 x i64> %a, ptr %b, i64 %c)
ret void
}
-declare void @llvm.ppc.vsx.stxvrl(<4 x i32>, ptr, i64)
+declare void @llvm.ppc.vsx.stxvrl.v2i64(<2 x i64>, ptr, i64)
-define void @testSTXVRLL(<4 x i32> %a, ptr %b, i64 %c) {
-; CHECK-LABEL: testSTXVRLL:
+define void @testSTXVRLL2(<2 x i64> %a, ptr %b, i64 %c) {
+; CHECK-LABEL: testSTXVRLL2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stxvrll v2, [[REG:r[0-9]+]], [[REG1:r[0-9]+]]
; CHECK: blr
entry:
- tail call void @llvm.ppc.vsx.stxvrll(<4 x i32> %a, ptr %b, i64 %c)
+ tail call void @llvm.ppc.vsx.stxvrll.v2i64(<2 x i64> %a, ptr %b, i64 %c)
ret void
}
-declare void @llvm.ppc.vsx.stxvrll(<4 x i32>, ptr, i64)
+declare void @llvm.ppc.vsx.stxvrll.v2i64(<2 x i64>, ptr, i64)
+
+; Test for load/store vectore pair.
+
+define <256 x i1> @testLXVPRL(ptr %vpp, i64 %b) {
+; CHECK-LABEL: testLXVPRL:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lxvprl vsp34, r4, r5
+; CHECK: blr
+entry:
+ %0 = tail call <256 x i1> @llvm.ppc.vsx.lxvprl(ptr %vpp, i64 %b)
+ ret <256 x i1> %0
+}
+declare <256 x i1> @llvm.ppc.vsx.lxvprl(ptr, i64)
+
+define <256 x i1> @testLXVPRLL(ptr %vpp, i64 %b) {
+; CHECK-LABEL: testLXVPRLL:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lxvprll vsp34, r4, r5
+; CHECK: blr
+entry:
+ %0 = tail call <256 x i1> @llvm.ppc.vsx.lxvprll(ptr %vpp, i64 %b)
+ ret <256 x i1> %0
+}
+declare <256 x i1> @llvm.ppc.vsx.lxvprll(ptr, i64)
define void @testSTXVPRL(ptr %v, ptr %vp, i64 %len) {
; CHECK-LABEL: testSTXVPRL:
>From 7910fe6e93b44e17003840b5a31c908e79f16564 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Tue, 15 Jul 2025 17:56:45 +0000
Subject: [PATCH 6/6] remove comments
---
llvm/lib/Target/PowerPC/PPCInstrFuture.td | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index 7c7627795420c..94028d82c2011 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -84,7 +84,6 @@ let Predicates = [HasVSX, IsISAFuture] in {
}
// Load/Store VSX Vector with Right Length Left-justified.
-// foreach Ty = [v4i32, v2i64, v128i1] in {
foreach Ty = [v4i32, v2i64] in {
def : Pat<(Ty (int_ppc_vsx_lxvrl addr:$RA, i64:$RB)),
(LXVRL memr:$RA, g8rc:$RB)>;
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