[llvm] [LLVM] Improve the DemandedBits Analysis (PR #148853)

[Yingwei Zheng via llvm-commits]

================
@@ -246,6 +247,59 @@ void DemandedBits::determineLiveOperandBits(
     else
       AB &= ~(Known.One & ~Known2.One);
     break;
+  case Instruction::SRem:
+  case Instruction::URem:
+  case Instruction::UDiv:
+  case Instruction::SDiv: {
+    auto Opc = UserI->getOpcode();
+    auto IsDiv = Opc == Instruction::UDiv || Opc == Instruction::SDiv;
+    bool IsSigned = Opc == Instruction::SDiv || Opc == Instruction::SRem;
+    if (OperandNo == 0) {
+      const APInt *DivAmnt;
+      if (match(UserI->getOperand(1), m_APInt(DivAmnt))) {
+        uint64_t D = DivAmnt->getZExtValue();
+        if (isPowerOf2_64(D)) {
+          unsigned Sh = Log2_64(D);
----------------
dtcxzyw wrote:

It will assert on div/rem with more than 64 bits. Please use APInt's API.
```suggestion
        if (DivAmnt->isPowerOf2()) {
          unsigned Sh = DivAmnt->countr_zero();
```

https://github.com/llvm/llvm-project/pull/148853