[llvm] [RISCV] Handle LHS == 0 in isVLKnownLE (PR #148860)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 15 07:45:05 PDT 2025
https://github.com/lukel97 created https://github.com/llvm/llvm-project/pull/148860
If a VL is zero then it's known to be less than or equal to every other VL.
This looks weird on its own since a VL of zero isn't that common. The test diffs come from a type being split resulting in a VP intrinsic's EVL being zero.
The motivation for this is to split off part of an upcoming patch I plan on submitting for RISCVVLOptimizer, which generalizes it to handle recurrences, and needs to reason about an initial state of demanded VLs set to zero.
>From 6797b51e52dbdee7f08ff137223aa4c8bce59d0f Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Tue, 15 Jul 2025 22:42:15 +0800
Subject: [PATCH] [RISCV] Handle LHS == 0 in isVLKnownLE
If a VL is zero then it's known to be less than or equal to every other VL.
This looks weird on its own since a VL of zero isn't that common. The test diffs come from a type being split resulting in a VP intrinsic's EVL being zero.
The motivation for this is to split off part of an upcoming patch I plan on submitting for RISCVVLOptimizer, which generalizes it to handle recurrences, and needs to reason about an initial state of demanded VLs set to zero.
---
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 2 ++
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll | 5 +++--
.../test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll | 5 +++--
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll | 11 ++++++-----
.../test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll | 11 ++++++-----
5 files changed, 20 insertions(+), 14 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index d3ade31740c7d..64f9e3eb8d86f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -4812,6 +4812,8 @@ bool RISCV::isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS) {
return true;
if (RHS.isImm() && RHS.getImm() == RISCV::VLMaxSentinel)
return true;
+ if (LHS.isImm() && LHS.getImm() == 0)
+ return true;
if (LHS.isImm() && LHS.getImm() == RISCV::VLMaxSentinel)
return false;
if (!LHS.isImm() || !RHS.isImm())
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
index 7afd31fdd663c..a04e31a19a4f1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
@@ -439,9 +439,10 @@ define <256 x i8> @vsadd_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
define <256 x i8> @vsadd_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
; CHECK-LABEL: vsadd_vi_v258i8_evl128:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 128
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v24, (a0)
+; CHECK-NEXT: li a0, 128
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
index f61b112fd8024..5556b11e9a90c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
@@ -435,9 +435,10 @@ define <256 x i8> @vsaddu_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
define <256 x i8> @vsaddu_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
; CHECK-LABEL: vsaddu_vi_v258i8_evl128:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 128
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v24, (a0)
+; CHECK-NEXT: li a0, 128
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
index 6ddf2e464750e..c28317bf14269 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
@@ -454,14 +454,15 @@ define <256 x i8> @vssub_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
define <256 x i8> @vssub_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
; CHECK-LABEL: vssub_vi_v258i8_evl128:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 128
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v24, (a0)
-; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: li a0, 128
+; CHECK-NEXT: li a1, -1
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
-; CHECK-NEXT: vssub.vx v16, v16, a0, v0.t
+; CHECK-NEXT: vssub.vx v16, v16, a1, v0.t
; CHECK-NEXT: ret
%v = call <256 x i8> @llvm.vp.ssub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128)
ret <256 x i8> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
index c403593894794..cbfe1292877ee 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
@@ -449,14 +449,15 @@ define <256 x i8> @vssubu_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
define <256 x i8> @vssubu_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
; CHECK-LABEL: vssubu_vi_v258i8_evl128:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 128
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v24, (a0)
-; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: li a0, 128
+; CHECK-NEXT: li a1, -1
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v16, v16, a0, v0.t
+; CHECK-NEXT: vssubu.vx v16, v16, a1, v0.t
; CHECK-NEXT: ret
%v = call <256 x i8> @llvm.vp.usub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128)
ret <256 x i8> %v
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