[llvm] [hexagon] Add support for llvm.thread.pointer (PR #148752)
Brian Cain via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 15 06:07:06 PDT 2025
https://github.com/androm3da updated https://github.com/llvm/llvm-project/pull/148752
>From 131480986d81cd9c38065b3d6ffb2b57b50b13b2 Mon Sep 17 00:00:00 2001
From: Brian Cain <brian.cain at oss.qualcomm.com>
Date: Mon, 14 Jul 2025 19:21:00 -0500
Subject: [PATCH 1/3] [hexagon] Add support for llvm.thread.pointer
---
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 14 +++++++++++++-
llvm/lib/Target/Hexagon/HexagonISelLowering.h | 1 +
llvm/lib/Target/Hexagon/HexagonPatterns.td | 5 +++++
llvm/test/CodeGen/Hexagon/thread-pointer.ll | 16 ++++++++++++++++
4 files changed, 35 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/Hexagon/thread-pointer.ll
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index ec73e58ce5d44..facea646d4b68 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -236,7 +236,16 @@ MVT HexagonTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
SDValue
HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
const {
- return SDValue();
+ unsigned IntNo = Op.getConstantOperandVal(0);
+ SDLoc dl(Op);
+ switch (IntNo) {
+ default:
+ return SDValue(); // Don't custom lower most intrinsics.
+ case Intrinsic::thread_pointer: {
+ EVT PtrVT = getPointerTy(DAG.getDataLayout());
+ return DAG.getNode(HexagonISD::THREAD_POINTER, dl, PtrVT);
+ }
+ }
}
/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
@@ -1588,6 +1597,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
setOperationAction(ISD::READSTEADYCOUNTER, MVT::i64, Custom);
+ setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
@@ -1963,6 +1973,8 @@ const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
case HexagonISD::VROR: return "HexagonISD::VROR";
case HexagonISD::READCYCLE: return "HexagonISD::READCYCLE";
case HexagonISD::READTIMER: return "HexagonISD::READTIMER";
+ case HexagonISD::THREAD_POINTER:
+ return "HexagonISD::THREAD_POINTER";
case HexagonISD::PTRUE: return "HexagonISD::PTRUE";
case HexagonISD::PFALSE: return "HexagonISD::PFALSE";
case HexagonISD::D2P: return "HexagonISD::D2P";
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
index f9e5478f457f8..3d329520d097a 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
@@ -78,6 +78,7 @@ enum NodeType : unsigned {
DCFETCH,
READCYCLE,
READTIMER,
+ THREAD_POINTER,
PTRUE,
PFALSE,
D2P, // Convert 8-byte value to 8-bit predicate register. [*]
diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td
index 82d999ad820ed..9b072bbacdbed 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatterns.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td
@@ -3432,6 +3432,11 @@ def HexagonREADTIMER: SDNode<"HexagonISD::READTIMER", SDTInt64Leaf,
def: Pat<(HexagonREADTIMER), (A4_tfrcpp UTIMER)>;
+def SDTInt32Leaf : SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>;
+def HexagonTHREADPOINTER : SDNode<"HexagonISD::THREAD_POINTER", SDTInt32Leaf>;
+
+def : Pat<(HexagonTHREADPOINTER), (i32(COPY UGP))>;
+
// The declared return value of the store-locked intrinsics is i32, but
// the instructions actually define i1. To avoid register copies from
// IntRegs to PredRegs and back, fold the entire pattern checking the
diff --git a/llvm/test/CodeGen/Hexagon/thread-pointer.ll b/llvm/test/CodeGen/Hexagon/thread-pointer.ll
new file mode 100644
index 0000000000000..cebb9ff3e202d
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/thread-pointer.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=hexagon < %s | FileCheck %s
+;
+; This test verifies the thread pointer intrinsic implementation for Hexagon.
+; The thread pointer (UGP register) is used to access thread-local storage.
+
+declare ptr @llvm.thread.pointer() nounwind readnone
+
+define ptr @thread_pointer() nounwind {
+; CHECK-LABEL: thread_pointer:
+; CHECK: // %bb.0:
+; CHECK: r0 = ugp
+; CHECK-NEXT: jumpr r31
+ %1 = tail call ptr @llvm.thread.pointer()
+ ret ptr %1
+}
>From cd390b39f19a3c7465a5c70312fe32466ea4e616 Mon Sep 17 00:00:00 2001
From: Brian Cain <brian.cain at oss.qualcomm.com>
Date: Mon, 14 Jul 2025 22:18:26 -0500
Subject: [PATCH 2/3] Fix from review
---
llvm/lib/Target/Hexagon/HexagonPatterns.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td
index 9b072bbacdbed..4b236708ca6d5 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatterns.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td
@@ -3433,7 +3433,7 @@ def HexagonREADTIMER: SDNode<"HexagonISD::READTIMER", SDTInt64Leaf,
def: Pat<(HexagonREADTIMER), (A4_tfrcpp UTIMER)>;
def SDTInt32Leaf : SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>;
-def HexagonTHREADPOINTER : SDNode<"HexagonISD::THREAD_POINTER", SDTInt32Leaf>;
+def HexagonTHREADPOINTER : SDNode<"HexagonISD::THREAD_POINTER", SDTPtrLeaf>;
def : Pat<(HexagonTHREADPOINTER), (i32(COPY UGP))>;
>From 31f8a759981d44f30d2a0f0f3c6cd422c6e42baf Mon Sep 17 00:00:00 2001
From: Brian Cain <brian.cain at oss.qualcomm.com>
Date: Tue, 15 Jul 2025 08:06:52 -0500
Subject: [PATCH 3/3] disable clang-format for the enum in order to avoid
re-formatting
---
llvm/lib/Target/Hexagon/HexagonISelLowering.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
index 3d329520d097a..9ebbbc6399b42 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
@@ -31,6 +31,7 @@ namespace llvm {
namespace HexagonISD {
+// clang-format off
enum NodeType : unsigned {
OP_BEGIN = ISD::BUILTIN_OP_END,
@@ -122,6 +123,7 @@ enum NodeType : unsigned {
};
} // end namespace HexagonISD
+// clang-format on
class HexagonSubtarget;
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