[llvm] [AArch64] Use correct regclass for spills of ZPR2/ZPR4 (PR #148806)

[Benjamin Maxwell via llvm-commits]

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@@ -2625,16 +2625,22 @@ let Predicates = [HasSVE_or_SME] in {
   // These get expanded to individual LDR_ZXI/STR_ZXI instructions in
   // AArch64ExpandPseudoInsts.
   let mayLoad = 1, hasSideEffects = 0 in {
-    def LDR_ZZXI   : Pseudo<(outs   ZZ_b_strided_and_contiguous:$Zd), (ins GPR64sp:$sp, simm4s1:$offset),[]>, Sched<[]>;
+    def LDR_ZZXI_STRIDED_CONTIGUOUS   : Pseudo<(outs   ZZ_b_strided_and_contiguous:$Zd), (ins GPR64sp:$sp, simm4s1:$offset),[]>, Sched<[]>;
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MacDue wrote:

nit: not all of this is this PR, but it bugs me that there's three different ways to refer to the same concept: 

- `strided_and_contiguous`
- `StridedOrContiguousRegClass`
- `STRIDED_CONTIGUOUS:`

(my vote is for "strided  or contiguous")

https://github.com/llvm/llvm-project/pull/148806