[llvm] [RISCV] Add ISel patterns for Qualcomm uC Xqcicli extension (PR #148121)

[Sam Elliott via llvm-commits]

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@@ -1485,6 +1501,36 @@ def : QCIMVCCIPat <SETLT,  QC_MVLTI, simm5>;
 def : QCIMVCCIPat <SETULT, QC_MVLTUI, uimm5>;
 }
 
+let Predicates = [HasVendorXqcicli, HasVendorXqcicsOrXqcicm, IsRV32] in {
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lenary wrote:

I advised towards this way because I felt our best aim was to try to keep to standard nodes (which is why i avoided `riscvisd::select_cc`), and to try to keep to what was mostly already happening in RISC-V (which is why i avoided `isd::select_cc`), but evidently that instinct isn't quite right.

I would like to proceed with this approach for this patch, and later we can refactor to `riscvisd::select_cc`, I think.



https://github.com/llvm/llvm-project/pull/148121