[llvm] [AArch64][Codegen]Transform saturating smull to sqdmulh (PR #143671)

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<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp -- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 820742b70..0b2813217 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -21001,7 +21001,8 @@ static SDValue trySQDMULHCombine(SDNode *N, SelectionDAG &DAG) {
 
   EVT DestVT = N->getValueType(0);
 
-  if (!DestVT.isVector() || DestVT.getScalarSizeInBits() > 64 || DestVT.isScalableVector())
+  if (!DestVT.isVector() || DestVT.getScalarSizeInBits() > 64 ||
+      DestVT.isScalableVector())
     return SDValue();
 
   ConstantSDNode *Clamp = isConstOrConstSplat(N->getOperand(1));
@@ -21050,8 +21051,7 @@ static SDValue trySQDMULHCombine(SDNode *N, SelectionDAG &DAG) {
   EVT SExt0Type = SExt0.getOperand(0).getValueType();
   EVT SExt1Type = SExt1.getOperand(0).getValueType();
 
-  if (SExt0Type != SExt1Type ||
-      SExt0Type.getScalarType() != ScalarType ||
+  if (SExt0Type != SExt1Type || SExt0Type.getScalarType() != ScalarType ||
       SExt0Type.getFixedSizeInBits() > 128)
     return SDValue();
 
@@ -21061,10 +21061,9 @@ static SDValue trySQDMULHCombine(SDNode *N, SelectionDAG &DAG) {
 
   // Ensure input vectors are extended to legal types
   if (SExt0Type.getFixedSizeInBits() < 64) {
-      unsigned VecNumElements = SExt0Type.getVectorNumElements();
-      EVT ExtVecVT =
-        MVT::getVectorVT(MVT::getIntegerVT(64 / VecNumElements),
-                         VecNumElements);
+    unsigned VecNumElements = SExt0Type.getVectorNumElements();
+    EVT ExtVecVT = MVT::getVectorVT(MVT::getIntegerVT(64 / VecNumElements),
+                                    VecNumElements);
     V0 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVecVT, V0);
     V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVecVT, V1);
   }

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https://github.com/llvm/llvm-project/pull/143671