[llvm] 6c2e26a - [LLVM][CodeGen] Ensure optimizeIncrementingWhile only accepts scalable vectors. (#148351)

[via llvm-commits]

Author: Paul Walker
Date: 2025-07-14T12:03:51+01:00
New Revision: 6c2e26aebf4633a65b45c438e811151a41f85e1f

URL: https://github.com/llvm/llvm-project/commit/6c2e26aebf4633a65b45c438e811151a41f85e1f
DIFF: https://github.com/llvm/llvm-project/commit/6c2e26aebf4633a65b45c438e811151a41f85e1f.diff

LOG: [LLVM][CodeGen] Ensure optimizeIncrementingWhile only accepts scalable vectors. (#148351)

Fixes https://github.com/llvm/llvm-project/issues/148347

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    llvm/test/CodeGen/AArch64/active_lane_mask.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index f7de61f044a7d..55601e6327e98 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -5512,7 +5512,8 @@ static SDValue optimizeIncrementingWhile(SDNode *N, SelectionDAG &DAG,
   unsigned Op0 = N->getOpcode() == ISD::INTRINSIC_WO_CHAIN ? 1 : 0;
   unsigned Op1 = N->getOpcode() == ISD::INTRINSIC_WO_CHAIN ? 2 : 1;
 
-  if (!isa<ConstantSDNode>(N->getOperand(Op1)))
+  if (!N->getValueType(0).isScalableVector() ||
+      !isa<ConstantSDNode>(N->getOperand(Op1)))
     return SDValue();
 
   SDLoc DL(N);

diff  --git a/llvm/test/CodeGen/AArch64/active_lane_mask.ll b/llvm/test/CodeGen/AArch64/active_lane_mask.ll
index cc05836d3d156..879dd4c12c0ba 100644
--- a/llvm/test/CodeGen/AArch64/active_lane_mask.ll
+++ b/llvm/test/CodeGen/AArch64/active_lane_mask.ll
@@ -460,6 +460,18 @@ entry:
   ret <vscale x 16 x i1> %active.lane.mask
 }
 
+define <8 x i1> @lane_mask_v8i1_imm3() {
+; CHECK-LABEL: lane_mask_v8i1_imm3:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ptrue p0.b, vl3
+; CHECK-NEXT:    mov z0.b, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; CHECK-NEXT:    ret
+entry:
+  %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 0, i64 3)
+  ret <8 x i1> %active.lane.mask
+}
+
 declare <vscale x 32 x i1> @llvm.get.active.lane.mask.nxv32i1.i32(i32, i32)
 declare <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i32(i32, i32)
 declare <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i32(i32, i32)