[llvm] [DAG] SelectionDAG::canCreateUndefOrPoison - Mark AVGFLOORS and AVGCEILS as safe (PR #148191)

[via llvm-commits]

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@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=arm64 -mcpu=apple-m1 | FileCheck %s
+
+; CHECK-LABEL: avg:
+; CHECK:       add
+; CHECK:       lsr
+; CHECK:       ret
+
+define zeroext i8 @avg(i8 noundef zeroext %a, i8 noundef zeroext %b) {
+entry:
+  %conv = zext i8 %a to i16
+  %conv1 = zext i8 %b to i16
+  %add = add nuw nsw i16 %conv1, %conv
+  %div3 = lshr i16 %add, 1
+  %conv2 = trunc nuw i16 %div3 to i8
+  ret i8 %conv2
+}
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aabhinavg1 wrote:

You're right, the src/tgt version highlights a more interesting optimization around freeze placement and known bits. As you mentioned, it doesn't work yet because support for ``AArch64ISD::MOVIshift`` is missing in ``computeKnownBitsForTargetNode`` .

What you said makes sense  we can look into adding that support in a follow-up patch. Once it's there, we can add the more advanced test to properly check how known bits interact with freeze.

For this patch, I suggest we go ahead with the current tests. They still serve the main purpose, which is to make sure that freeze after hadd/rhadd doesn't interfere with instruction selection.

Let me know if you're good with that. If yes, we can land this one and open a new patch for the MOVIshift support and the src/tgt test.

https://github.com/llvm/llvm-project/pull/148191