[llvm] [DAG] SelectionDAG::canCreateUndefOrPoison - Mark AVGFLOORS and AVGCEILS as safe (PR #148191)

[via llvm-commits]

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@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=arm64 -mcpu=apple-m1 | FileCheck %s
+
+; CHECK-LABEL: avg:
+; CHECK:       add
+; CHECK:       lsr
+; CHECK:       ret
+
+define zeroext i8 @avg(i8 noundef zeroext %a, i8 noundef zeroext %b) {
+entry:
+  %conv = zext i8 %a to i16
+  %conv1 = zext i8 %b to i16
+  %add = add nuw nsw i16 %conv1, %conv
+  %div3 = lshr i16 %add, 1
+  %conv2 = trunc nuw i16 %div3 to i8
+  ret i8 %conv2
+}
----------------
aabhinavg1 wrote:

Hi @RKSimon 
 I've now added a separate AArch64 test (avg-freeze.ll) that demonstrates freeze applied after the ``hadd/rhadd ``intrinsics ``(shadd, srhadd, uhadd, urhadd)``. This avoids blocking instruction selection and ensures correctness. The tests include:
- freeze_shadd_vec
- freeze_srhadd_vec
- freeze_uhadd_vec
- freeze_urhadd_vec

> The logic is similar to how freeze-preserving intrinsic selection is handled in ``freeze-binary.ll`` for ``X86``.
<details>
<summary><strong>testcase</strong></summary>

```python
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=AARCH64

; This test verifies that applying `freeze` to the result of AArch64 hadd/rhadd intrinsics
; does not interfere with instruction selection.
; The intrinsic is computed first, then frozen. Since `freeze` is applied after,
; it does not block the selection of `shadd`, `srhadd`, `uhadd`, or `urhadd`.

declare <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16>, <8 x i16>)
declare <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16>, <8 x i16>)
declare <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16>, <8 x i16>)
declare <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16>, <8 x i16>)

define <8 x i16> @freeze_shadd_vec(<8 x i16> %a, <8 x i16> %b) {
; AARCH64-LABEL: freeze_shadd_vec:
; AARCH64:       shadd v0.8h, v0.8h, v1.8h
; AARCH64-NEXT:  ret
  %avg = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> %a, <8 x i16> %b)
  %frozen = freeze <8 x i16> %avg
  ret <8 x i16> %frozen
}

define <8 x i16> @freeze_srhadd_vec(<8 x i16> %a, <8 x i16> %b) {
; AARCH64-LABEL: freeze_srhadd_vec:
; AARCH64:       srhadd v0.8h, v0.8h, v1.8h
; AARCH64-NEXT:  ret
  %avg = call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> %a, <8 x i16> %b)
  %frozen = freeze <8 x i16> %avg
  ret <8 x i16> %frozen
}

define <8 x i16> @freeze_uhadd_vec(<8 x i16> %a, <8 x i16> %b) {
; AARCH64-LABEL: freeze_uhadd_vec:
; AARCH64:       uhadd v0.8h, v0.8h, v1.8h
; AARCH64-NEXT:  ret
  %avg = call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> %a, <8 x i16> %b)
  %frozen = freeze <8 x i16> %avg
  ret <8 x i16> %frozen
}

define <8 x i16> @freeze_urhadd_vec(<8 x i16> %a, <8 x i16> %b) {
; AARCH64-LABEL: freeze_urhadd_vec:
; AARCH64:       urhadd v0.8h, v0.8h, v1.8h
; AARCH64-NEXT:  ret
  %avg = call <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16> %a, <8 x i16> %b)
  %frozen = freeze <8 x i16> %avg
  ret <8 x i16> %frozen
}

```
</details>

<details>
<summary><strong>  llvm-lit report </strong></summary>

```python
./llvm-lit ../../llvm/test/CodeGen/AArch64/avg-freeze.ll

-- Testing: 1 tests, 1 workers --
PASS: LLVM :: CodeGen/AArch64/avg-freeze.ll (1 of 1)

Testing Time: 0.16s

Total Discovered Tests: 1
  Passed: 1 (100.00%)
```
</details>

> Let me know if you'd like to see this added to a different file or want to keep a different name for the file coverage!
> or i need to modify anything in the testcase

https://github.com/llvm/llvm-project/pull/148191