[llvm] [InstCombine] Optimize (select %x, op(%x), 0) to op(%x) for operations where op(0) == 0 (PR #147605)
Ryan Buchner via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 14 02:06:48 PDT 2025
https://github.com/bababuck updated https://github.com/llvm/llvm-project/pull/147605
>From 01da92dc1af0bb73db1518ff814f8716e1e2e983 Mon Sep 17 00:00:00 2001
From: Ryan Buchner <rbuchner at ventanamicro.com>
Date: Tue, 1 Jul 2025 14:00:48 -0700
Subject: [PATCH 1/7] Add tests for cases with (select %x, op(%x), 0) for
operations where op(0) == 0
These cases can be optimized to just op(%x).
---
.../InstCombine/select-fixed-zero.ll | 207 ++++++++++++++++++
1 file changed, 207 insertions(+)
create mode 100644 llvm/test/Transforms/InstCombine/select-fixed-zero.ll
diff --git a/llvm/test/Transforms/InstCombine/select-fixed-zero.ll b/llvm/test/Transforms/InstCombine/select-fixed-zero.ll
new file mode 100644
index 0000000000000..c16497fd7cffe
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/select-fixed-zero.ll
@@ -0,0 +1,207 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -passes=instcombine < %s | FileCheck %s
+
+; (select (icmp x, 0, eq), 0, (umin x, y)) -> (umin x, y)
+define i64 @umin_select(i64 %a, i64 %b) {
+; CHECK-LABEL: @umin_select(
+; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[A:%.*]], 0
+; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[A]], i64 [[B_FR:%.*]])
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], i64 0, i64 [[UMIN]]
+; CHECK-NEXT: ret i64 [[SELECT]]
+;
+ %cond = icmp eq i64 %a, 0
+ %umin = call i64 @llvm.umin.i64(i64 %a, i64 %b)
+ %select = select i1 %cond, i64 0, i64 %umin
+ ret i64 %select
+}
+
+; (select (icmp x, 0, eq), 0, (mul x, y)) -> (mul x, y)
+define i64 @mul_select(i64 %a, i64 %b) {
+; CHECK-LABEL: @mul_select(
+; CHECK-NEXT: [[B_FR:%.*]] = freeze i64 [[B:%.*]]
+; CHECK-NEXT: [[MUL:%.*]] = mul i64 [[A:%.*]], [[B_FR]]
+; CHECK-NEXT: ret i64 [[MUL]]
+;
+ %cond = icmp eq i64 %a, 0
+ %mul = mul i64 %a, %b
+ %select = select i1 %cond, i64 0, i64 %mul
+ ret i64 %select
+}
+
+; (select (icmp x, 0, eq), 0, (shl x, y)) -> (shl x, y)
+define i64 @shl_select(i64 %a, i64 %b) {
+; CHECK-LABEL: @shl_select(
+; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[A:%.*]], 0
+; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[A]], [[B_FR:%.*]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], i64 0, i64 [[SHL]]
+; CHECK-NEXT: ret i64 [[SELECT]]
+;
+ %cond = icmp eq i64 %a, 0
+ %shl = shl i64 %a, %b
+ %select = select i1 %cond, i64 0, i64 %shl
+ ret i64 %select
+}
+
+; (select (icmp x, 0, eq), 0, (and x, y)) -> (and x, y)
+define i64 @and_select(i64 %a, i64 %b) {
+; CHECK-LABEL: @and_select(
+; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[A:%.*]], 0
+; CHECK-NEXT: [[AND:%.*]] = and i64 [[A]], [[B_FR:%.*]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], i64 0, i64 [[AND]]
+; CHECK-NEXT: ret i64 [[SELECT]]
+;
+ %cond = icmp eq i64 %a, 0
+ %and = and i64 %a, %b
+ %select = select i1 %cond, i64 0, i64 %and
+ ret i64 %select
+}
+
+; (select (icmp x, 0, ne), (ashr x, y), 0) -> (ashr x, y)
+define i64 @ashr_select(i64 %a, i64 %b) {
+; CHECK-LABEL: @ashr_select(
+; CHECK-NEXT: [[COND_NOT:%.*]] = icmp eq i64 [[A:%.*]], 0
+; CHECK-NEXT: [[ASHR:%.*]] = ashr i64 [[A]], [[B_FR:%.*]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND_NOT]], i64 0, i64 [[ASHR]]
+; CHECK-NEXT: ret i64 [[SELECT]]
+;
+ %cond = icmp ne i64 0, %a
+ %ashr = ashr i64 %a, %b
+ %select = select i1 %cond, i64 %ashr, i64 0
+ ret i64 %select
+}
+
+; (select (icmp x, 0, ne), (lshr x, y), 0) -> (lshr x, y)
+define i64 @lshr_select(i64 %a, i64 %b) {
+; CHECK-LABEL: @lshr_select(
+; CHECK-NEXT: [[COND_NOT:%.*]] = icmp eq i64 [[A:%.*]], 0
+; CHECK-NEXT: [[LSHR:%.*]] = lshr i64 [[A]], [[B_FR:%.*]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND_NOT]], i64 0, i64 [[LSHR]]
+; CHECK-NEXT: ret i64 [[SELECT]]
+;
+ %cond = icmp ne i64 0, %a
+ %lshr = lshr i64 %a, %b
+ %select = select i1 %cond, i64 %lshr, i64 0
+ ret i64 %select
+}
+
+; (select (icmp x, 0, eq), 0, fshr(x, x, y)) -> fshr(x, x, y)
+define i64 @fshr_select(i64 %a, i64 %b) {
+; CHECK-LABEL: @fshr_select(
+; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[A:%.*]], 0
+; CHECK-NEXT: [[FSHR:%.*]] = call i64 @llvm.fshr.i64(i64 [[A]], i64 [[A]], i64 [[B_FR:%.*]])
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], i64 0, i64 [[FSHR]]
+; CHECK-NEXT: ret i64 [[SELECT]]
+;
+ %cond = icmp eq i64 %a, 0
+ %fshr = call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %b)
+ %select = select i1 %cond, i64 0, i64 %fshr
+ ret i64 %select
+}
+
+; (select (icmp x, 0, eq), 0, (fshl x, x, y)) -> (fshl x, x, y)
+define i64 @fshl_select(i64 %a, i64 %b) {
+; CHECK-LABEL: @fshl_select(
+; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[A:%.*]], 0
+; CHECK-NEXT: [[FSHL:%.*]] = call i64 @llvm.fshl.i64(i64 [[A]], i64 [[A]], i64 [[B_FR:%.*]])
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], i64 0, i64 [[FSHL]]
+; CHECK-NEXT: ret i64 [[SELECT]]
+;
+ %cond = icmp eq i64 %a, 0
+ %fshl = call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %b)
+ %select = select i1 %cond, i64 0, i64 %fshl
+ ret i64 %select
+}
+
+; (select (icmp x, 0, eq), 0, (fshr x, z, y)) -> leave as is
+define i64 @fshr_select_no_combine(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: @fshr_select_no_combine(
+; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[A:%.*]], 0
+; CHECK-NEXT: [[FSHR:%.*]] = call i64 @llvm.fshr.i64(i64 [[A]], i64 [[B:%.*]], i64 [[C:%.*]])
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], i64 0, i64 [[FSHR]]
+; CHECK-NEXT: ret i64 [[SELECT]]
+;
+ %cond = icmp eq i64 %a, 0
+ %fshr = call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 %c)
+ %select = select i1 %cond, i64 0, i64 %fshr
+ ret i64 %select
+}
+
+; (select (icmp x, 0, eq), 0, (sdiv x, y)) -> (sdiv x, y)
+define i64 @sdiv_select(i64 %a, i64 %b) {
+; CHECK-LABEL: @sdiv_select(
+; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[A:%.*]], 0
+; CHECK-NEXT: [[DIV:%.*]] = sdiv i64 [[A]], [[B_FR:%.*]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], i64 0, i64 [[DIV]]
+; CHECK-NEXT: ret i64 [[SELECT]]
+;
+ %cond = icmp eq i64 %a, 0
+ %div = sdiv i64 %a, %b
+ %select = select i1 %cond, i64 0, i64 %div
+ ret i64 %select
+}
+
+; (select (icmp x, 0, eq), 0, (udiv x, y)) -> (udiv x, y)
+define i64 @udiv_select(i64 %a, i64 %b) {
+; CHECK-LABEL: @udiv_select(
+; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[A:%.*]], 0
+; CHECK-NEXT: [[DIV:%.*]] = udiv i64 [[A]], [[B_FR:%.*]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], i64 0, i64 [[DIV]]
+; CHECK-NEXT: ret i64 [[SELECT]]
+;
+ %cond = icmp eq i64 %a, 0
+ %div = udiv i64 %a, %b
+ %select = select i1 %cond, i64 0, i64 %div
+ ret i64 %select
+}
+
+; (select (icmp x, 0, eq), 0, (srem x, y)) -> (srem x, y)
+define i64 @srem_select(i64 %a, i64 %b) {
+; CHECK-LABEL: @srem_select(
+; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[A:%.*]], 0
+; CHECK-NEXT: [[REM:%.*]] = srem i64 [[A]], [[B:%.*]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], i64 0, i64 [[REM]]
+; CHECK-NEXT: ret i64 [[SELECT]]
+;
+ %cond = icmp eq i64 %a, 0
+ %rem = srem i64 %a, %b
+ %select = select i1 %cond, i64 0, i64 %rem
+ ret i64 %select
+}
+
+; (select (icmp x, 0, eq), 0, (urem x, y)) -> (urem x, y)
+define i64 @urem_select(i64 %a, i64 %b) {
+; CHECK-LABEL: @urem_select(
+; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[A:%.*]], 0
+; CHECK-NEXT: [[REM:%.*]] = urem i64 [[A]], [[B:%.*]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], i64 0, i64 [[REM]]
+; CHECK-NEXT: ret i64 [[SELECT]]
+;
+ %cond = icmp eq i64 %a, 0
+ %rem = urem i64 %a, %b
+ %select = select i1 %cond, i64 0, i64 %rem
+ ret i64 %select
+}
+
+; (select (icmp x, 0, eq), 0, (icmp x, 0, slt)) -> (icmp x, 0, slt)
+define i1 @icmp_slt_select(i64 %a) {
+; CHECK-LABEL: @icmp_slt_select(
+; CHECK-NEXT: [[ICMP:%.*]] = icmp slt i64 [[A:%.*]], 0
+; CHECK-NEXT: ret i1 [[ICMP]]
+;
+ %cond = icmp eq i64 %a, 0
+ %icmp = icmp slt i64 %a, 0
+ %select = select i1 %cond, i1 0, i1 %icmp
+ ret i1 %select
+}
+
+; (select (icmp x, 0, eq), 0, (sub 0, x)) -> (sub 0, x)
+define i64 @sub_select(i64 %a) {
+; CHECK-LABEL: @sub_select(
+; CHECK-NEXT: [[SUB:%.*]] = sub i64 0, [[A:%.*]]
+; CHECK-NEXT: ret i64 [[SUB]]
+;
+ %cond = icmp eq i64 %a, 0
+ %sub = sub i64 0, %a
+ %select = select i1 %cond, i64 0, i64 %sub
+ ret i64 %select
+}
>From f014465f2a41d93a4efcb4fb6ba96257de25247e Mon Sep 17 00:00:00 2001
From: Ryan Buchner <rbuchner at ventanamicro.com>
Date: Tue, 1 Jul 2025 14:06:33 -0700
Subject: [PATCH 2/7] [InstCombine] Optimize (select %x, op(%x), 0) to op(%x)
for operations where op(0) == 0
Have to freeze the any other operands to prevent poisons from leaking. Re-uses
flow from `mul` specific version of this within the InstCombie pass.
---
.../InstCombine/InstCombineSelect.cpp | 39 +++++++++---
.../Transforms/InstCombine/icmp-select.ll | 7 +--
.../InstCombine/select-fixed-zero.ll | 63 ++++++++-----------
llvm/test/Transforms/InstCombine/select.ll | 14 ++---
4 files changed, 65 insertions(+), 58 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
index 73ba0f78e8053..023ca5245f494 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
@@ -878,7 +878,11 @@ static Instruction *foldSetClearBits(SelectInst &Sel,
// is a vector consisting of 0 and undefs. If a constant compared with x
// is a scalar undefined value or undefined vector then an expression
// should be already folded into a constant.
-static Instruction *foldSelectZeroOrMul(SelectInst &SI, InstCombinerImpl &IC) {
+//
+// This also holds all operations such that Op(0) == 0
+// e.g. Shl, Umin, etc
+static Instruction *foldSelectZeroOrFixedOp(SelectInst &SI,
+ InstCombinerImpl &IC) {
auto *CondVal = SI.getCondition();
auto *TrueVal = SI.getTrueValue();
auto *FalseVal = SI.getFalseValue();
@@ -900,9 +904,7 @@ static Instruction *foldSelectZeroOrMul(SelectInst &SI, InstCombinerImpl &IC) {
// non-zero elements that are masked by undef elements in the compare
// constant.
auto *TrueValC = dyn_cast<Constant>(TrueVal);
- if (TrueValC == nullptr ||
- !match(FalseVal, m_c_Mul(m_Specific(X), m_Value(Y))) ||
- !isa<Instruction>(FalseVal))
+ if (TrueValC == nullptr || !isa<Instruction>(FalseVal))
return nullptr;
auto *ZeroC = cast<Constant>(cast<Instruction>(CondVal)->getOperand(1));
@@ -913,11 +915,28 @@ static Instruction *foldSelectZeroOrMul(SelectInst &SI, InstCombinerImpl &IC) {
if (!match(MergedC, m_Zero()) && !match(MergedC, m_Undef()))
return nullptr;
- auto *FalseValI = cast<Instruction>(FalseVal);
- auto *FrY = IC.InsertNewInstBefore(new FreezeInst(Y, Y->getName() + ".fr"),
- FalseValI->getIterator());
- IC.replaceOperand(*FalseValI, FalseValI->getOperand(0) == Y ? 0 : 1, FrY);
- return IC.replaceInstUsesWith(SI, FalseValI);
+ if (match(FalseVal, m_c_Mul(m_Specific(X), m_Value(Y))) ||
+ match(FalseVal, m_c_And(m_Specific(X), m_Value(Y))) ||
+ match(FalseVal, m_Shl(m_Specific(X), m_Value(Y))) ||
+ match(FalseVal, m_AShr(m_Specific(X), m_Value(Y))) ||
+ match(FalseVal, m_LShr(m_Specific(X), m_Value(Y))) ||
+ match(FalseVal, m_FShl(m_Specific(X), m_Specific(X), m_Value(Y))) ||
+ match(FalseVal, m_FShr(m_Specific(X), m_Specific(X), m_Value(Y))) ||
+ match(FalseVal, m_SDiv(m_Specific(X), m_Value(Y))) ||
+ match(FalseVal, m_UDiv(m_Specific(X), m_Value(Y))) ||
+ match(FalseVal, m_c_UMin(m_Specific(X), m_Value(Y)))) {
+ auto *FalseValI = cast<Instruction>(FalseVal);
+ auto *FrY = IC.InsertNewInstBefore(new FreezeInst(Y, Y->getName() + ".fr"),
+ FalseValI->getIterator());
+ IC.replaceOperand(*FalseValI,
+ FalseValI->getOperand(0) == Y
+ ? 0
+ : (FalseValI->getOperand(1) == Y ? 1 : 2),
+ FrY);
+ return IC.replaceInstUsesWith(SI, FalseValI);
+ }
+
+ return nullptr;
}
/// Transform patterns such as (a > b) ? a - b : 0 into usub.sat(a, b).
@@ -4104,7 +4123,7 @@ Instruction *InstCombinerImpl::visitSelectInst(SelectInst &SI) {
return Add;
if (Instruction *Or = foldSetClearBits(SI, Builder))
return Or;
- if (Instruction *Mul = foldSelectZeroOrMul(SI, *this))
+ if (Instruction *Mul = foldSelectZeroOrFixedOp(SI, *this))
return Mul;
// Turn (select C, (op X, Y), (op X, Z)) -> (op X, (select C, Y, Z))
diff --git a/llvm/test/Transforms/InstCombine/icmp-select.ll b/llvm/test/Transforms/InstCombine/icmp-select.ll
index a038731abbc48..c6c0ba385a6fd 100644
--- a/llvm/test/Transforms/InstCombine/icmp-select.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-select.ll
@@ -248,10 +248,9 @@ define i1 @icmp_select_implied_cond_relational_off_by_one(i8 %x, i8 %y) {
define i1 @umin_seq_comparison(i8 %x, i8 %y) {
; CHECK-LABEL: @umin_seq_comparison(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[X:%.*]], 0
-; CHECK-NEXT: [[CMP21:%.*]] = icmp ule i8 [[X]], [[Y:%.*]]
-; CHECK-NEXT: [[CMP2:%.*]] = select i1 [[CMP1]], i1 true, i1 [[CMP21]]
-; CHECK-NEXT: ret i1 [[CMP2]]
+; CHECK-NEXT: [[Y:%.*]] = freeze i8 [[Y1:%.*]]
+; CHECK-NEXT: [[CMP21:%.*]] = icmp ule i8 [[X:%.*]], [[Y]]
+; CHECK-NEXT: ret i1 [[CMP21]]
;
%min = call i8 @llvm.umin.i8(i8 %x, i8 %y)
%cmp1 = icmp eq i8 %x, 0
diff --git a/llvm/test/Transforms/InstCombine/select-fixed-zero.ll b/llvm/test/Transforms/InstCombine/select-fixed-zero.ll
index c16497fd7cffe..27a404ad2c8bd 100644
--- a/llvm/test/Transforms/InstCombine/select-fixed-zero.ll
+++ b/llvm/test/Transforms/InstCombine/select-fixed-zero.ll
@@ -4,10 +4,9 @@
; (select (icmp x, 0, eq), 0, (umin x, y)) -> (umin x, y)
define i64 @umin_select(i64 %a, i64 %b) {
; CHECK-LABEL: @umin_select(
-; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[A:%.*]], 0
-; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[A]], i64 [[B_FR:%.*]])
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], i64 0, i64 [[UMIN]]
-; CHECK-NEXT: ret i64 [[SELECT]]
+; CHECK-NEXT: [[B_FR:%.*]] = freeze i64 [[B:%.*]]
+; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[A:%.*]], i64 [[B_FR]])
+; CHECK-NEXT: ret i64 [[UMIN]]
;
%cond = icmp eq i64 %a, 0
%umin = call i64 @llvm.umin.i64(i64 %a, i64 %b)
@@ -31,10 +30,9 @@ define i64 @mul_select(i64 %a, i64 %b) {
; (select (icmp x, 0, eq), 0, (shl x, y)) -> (shl x, y)
define i64 @shl_select(i64 %a, i64 %b) {
; CHECK-LABEL: @shl_select(
-; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[A:%.*]], 0
-; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[A]], [[B_FR:%.*]]
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], i64 0, i64 [[SHL]]
-; CHECK-NEXT: ret i64 [[SELECT]]
+; CHECK-NEXT: [[B_FR:%.*]] = freeze i64 [[B:%.*]]
+; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[A:%.*]], [[B_FR]]
+; CHECK-NEXT: ret i64 [[SHL]]
;
%cond = icmp eq i64 %a, 0
%shl = shl i64 %a, %b
@@ -45,10 +43,9 @@ define i64 @shl_select(i64 %a, i64 %b) {
; (select (icmp x, 0, eq), 0, (and x, y)) -> (and x, y)
define i64 @and_select(i64 %a, i64 %b) {
; CHECK-LABEL: @and_select(
-; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[A:%.*]], 0
-; CHECK-NEXT: [[AND:%.*]] = and i64 [[A]], [[B_FR:%.*]]
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], i64 0, i64 [[AND]]
-; CHECK-NEXT: ret i64 [[SELECT]]
+; CHECK-NEXT: [[B_FR:%.*]] = freeze i64 [[B:%.*]]
+; CHECK-NEXT: [[AND:%.*]] = and i64 [[A:%.*]], [[B_FR]]
+; CHECK-NEXT: ret i64 [[AND]]
;
%cond = icmp eq i64 %a, 0
%and = and i64 %a, %b
@@ -59,10 +56,9 @@ define i64 @and_select(i64 %a, i64 %b) {
; (select (icmp x, 0, ne), (ashr x, y), 0) -> (ashr x, y)
define i64 @ashr_select(i64 %a, i64 %b) {
; CHECK-LABEL: @ashr_select(
-; CHECK-NEXT: [[COND_NOT:%.*]] = icmp eq i64 [[A:%.*]], 0
-; CHECK-NEXT: [[ASHR:%.*]] = ashr i64 [[A]], [[B_FR:%.*]]
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND_NOT]], i64 0, i64 [[ASHR]]
-; CHECK-NEXT: ret i64 [[SELECT]]
+; CHECK-NEXT: [[B_FR:%.*]] = freeze i64 [[B:%.*]]
+; CHECK-NEXT: [[ASHR:%.*]] = ashr i64 [[A:%.*]], [[B_FR]]
+; CHECK-NEXT: ret i64 [[ASHR]]
;
%cond = icmp ne i64 0, %a
%ashr = ashr i64 %a, %b
@@ -73,10 +69,9 @@ define i64 @ashr_select(i64 %a, i64 %b) {
; (select (icmp x, 0, ne), (lshr x, y), 0) -> (lshr x, y)
define i64 @lshr_select(i64 %a, i64 %b) {
; CHECK-LABEL: @lshr_select(
-; CHECK-NEXT: [[COND_NOT:%.*]] = icmp eq i64 [[A:%.*]], 0
-; CHECK-NEXT: [[LSHR:%.*]] = lshr i64 [[A]], [[B_FR:%.*]]
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND_NOT]], i64 0, i64 [[LSHR]]
-; CHECK-NEXT: ret i64 [[SELECT]]
+; CHECK-NEXT: [[B_FR:%.*]] = freeze i64 [[B:%.*]]
+; CHECK-NEXT: [[LSHR:%.*]] = lshr i64 [[A:%.*]], [[B_FR]]
+; CHECK-NEXT: ret i64 [[LSHR]]
;
%cond = icmp ne i64 0, %a
%lshr = lshr i64 %a, %b
@@ -87,10 +82,9 @@ define i64 @lshr_select(i64 %a, i64 %b) {
; (select (icmp x, 0, eq), 0, fshr(x, x, y)) -> fshr(x, x, y)
define i64 @fshr_select(i64 %a, i64 %b) {
; CHECK-LABEL: @fshr_select(
-; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[A:%.*]], 0
-; CHECK-NEXT: [[FSHR:%.*]] = call i64 @llvm.fshr.i64(i64 [[A]], i64 [[A]], i64 [[B_FR:%.*]])
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], i64 0, i64 [[FSHR]]
-; CHECK-NEXT: ret i64 [[SELECT]]
+; CHECK-NEXT: [[B_FR:%.*]] = freeze i64 [[B:%.*]]
+; CHECK-NEXT: [[FSHR:%.*]] = call i64 @llvm.fshr.i64(i64 [[A:%.*]], i64 [[A]], i64 [[B_FR]])
+; CHECK-NEXT: ret i64 [[FSHR]]
;
%cond = icmp eq i64 %a, 0
%fshr = call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %b)
@@ -101,10 +95,9 @@ define i64 @fshr_select(i64 %a, i64 %b) {
; (select (icmp x, 0, eq), 0, (fshl x, x, y)) -> (fshl x, x, y)
define i64 @fshl_select(i64 %a, i64 %b) {
; CHECK-LABEL: @fshl_select(
-; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[A:%.*]], 0
-; CHECK-NEXT: [[FSHL:%.*]] = call i64 @llvm.fshl.i64(i64 [[A]], i64 [[A]], i64 [[B_FR:%.*]])
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], i64 0, i64 [[FSHL]]
-; CHECK-NEXT: ret i64 [[SELECT]]
+; CHECK-NEXT: [[B_FR:%.*]] = freeze i64 [[B:%.*]]
+; CHECK-NEXT: [[FSHL:%.*]] = call i64 @llvm.fshl.i64(i64 [[A:%.*]], i64 [[A]], i64 [[B_FR]])
+; CHECK-NEXT: ret i64 [[FSHL]]
;
%cond = icmp eq i64 %a, 0
%fshl = call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %b)
@@ -129,10 +122,9 @@ define i64 @fshr_select_no_combine(i64 %a, i64 %b, i64 %c) {
; (select (icmp x, 0, eq), 0, (sdiv x, y)) -> (sdiv x, y)
define i64 @sdiv_select(i64 %a, i64 %b) {
; CHECK-LABEL: @sdiv_select(
-; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[A:%.*]], 0
-; CHECK-NEXT: [[DIV:%.*]] = sdiv i64 [[A]], [[B_FR:%.*]]
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], i64 0, i64 [[DIV]]
-; CHECK-NEXT: ret i64 [[SELECT]]
+; CHECK-NEXT: [[B_FR:%.*]] = freeze i64 [[B:%.*]]
+; CHECK-NEXT: [[DIV:%.*]] = sdiv i64 [[A:%.*]], [[B_FR]]
+; CHECK-NEXT: ret i64 [[DIV]]
;
%cond = icmp eq i64 %a, 0
%div = sdiv i64 %a, %b
@@ -143,10 +135,9 @@ define i64 @sdiv_select(i64 %a, i64 %b) {
; (select (icmp x, 0, eq), 0, (udiv x, y)) -> (udiv x, y)
define i64 @udiv_select(i64 %a, i64 %b) {
; CHECK-LABEL: @udiv_select(
-; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[A:%.*]], 0
-; CHECK-NEXT: [[DIV:%.*]] = udiv i64 [[A]], [[B_FR:%.*]]
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], i64 0, i64 [[DIV]]
-; CHECK-NEXT: ret i64 [[SELECT]]
+; CHECK-NEXT: [[B_FR:%.*]] = freeze i64 [[B:%.*]]
+; CHECK-NEXT: [[DIV:%.*]] = udiv i64 [[A:%.*]], [[B_FR]]
+; CHECK-NEXT: ret i64 [[DIV]]
;
%cond = icmp eq i64 %a, 0
%div = udiv i64 %a, %b
diff --git a/llvm/test/Transforms/InstCombine/select.ll b/llvm/test/Transforms/InstCombine/select.ll
index ef5874ffd46ad..fa54b38d55171 100644
--- a/llvm/test/Transforms/InstCombine/select.ll
+++ b/llvm/test/Transforms/InstCombine/select.ll
@@ -893,10 +893,9 @@ define i32 @test56(i16 %x) {
define i32 @test57(i32 %x, i32 %y) {
; CHECK-LABEL: @test57(
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[X]], 0
-; CHECK-NEXT: [[DOTAND:%.*]] = select i1 [[TOBOOL]], i32 0, i32 [[AND]]
-; CHECK-NEXT: ret i32 [[DOTAND]]
+; CHECK-NEXT: [[Y:%.*]] = freeze i32 [[Y1:%.*]]
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[Y]]
+; CHECK-NEXT: ret i32 [[AND]]
;
%and = and i32 %x, %y
%tobool = icmp eq i32 %x, 0
@@ -2734,10 +2733,9 @@ define void @select_freeze_icmp_multuses(i32 %x, i32 %y) {
define i32 @pr47322_more_poisonous_replacement(i32 %arg) {
; CHECK-LABEL: @pr47322_more_poisonous_replacement(
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[ARG:%.*]], 0
-; CHECK-NEXT: [[TRAILING:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[ARG]], i1 true)
-; CHECK-NEXT: [[SHIFTED:%.*]] = lshr exact i32 [[ARG]], [[TRAILING]]
-; CHECK-NEXT: [[R1_SROA_0_1:%.*]] = select i1 [[CMP]], i32 0, i32 [[SHIFTED]]
+; CHECK-NEXT: [[TRAILING:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[ARG:%.*]], i1 true)
+; CHECK-NEXT: [[TRAILING_FR:%.*]] = freeze i32 [[TRAILING]]
+; CHECK-NEXT: [[R1_SROA_0_1:%.*]] = lshr exact i32 [[ARG]], [[TRAILING_FR]]
; CHECK-NEXT: ret i32 [[R1_SROA_0_1]]
;
%cmp = icmp eq i32 %arg, 0
>From 63cfbe20185440775ff364ad691356d105b2037f Mon Sep 17 00:00:00 2001
From: bababuck <buchner.ryan at gmail.com>
Date: Wed, 9 Jul 2025 11:49:29 -0700
Subject: [PATCH 3/7] Reorder so that matching occurs before any data
extraction
Fixes bug in optimizing:
```
define <2 x i64> @php_url_encode_impl(i32 %0, ptr %p) {
%2 = load <2 x i64>, ptr %p, align 16
%.not = icmp eq i32 %0, 0
%spec.select = select i1 %.not, <2 x i64> zeroinitializer, <2 x i64> %2
ret <2 x i64> %spec.select
}
```
One side effect of the matching is that it garuntees that the types of the TrueV and the Conditional constant match which is assumed by the later code.
---
.../InstCombine/InstCombineSelect.cpp | 44 +++++++++----------
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
index 023ca5245f494..13cfaf54068b4 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
@@ -907,6 +907,19 @@ static Instruction *foldSelectZeroOrFixedOp(SelectInst &SI,
if (TrueValC == nullptr || !isa<Instruction>(FalseVal))
return nullptr;
+ if (!(match(FalseVal, m_c_Mul(m_Specific(X), m_Value(Y))) ||
+ match(FalseVal, m_c_And(m_Specific(X), m_Value(Y))) ||
+ match(FalseVal, m_Shl(m_Specific(X), m_Value(Y))) ||
+ match(FalseVal, m_AShr(m_Specific(X), m_Value(Y))) ||
+ match(FalseVal, m_LShr(m_Specific(X), m_Value(Y))) ||
+ match(FalseVal, m_FShl(m_Specific(X), m_Specific(X), m_Value(Y))) ||
+ match(FalseVal, m_FShr(m_Specific(X), m_Specific(X), m_Value(Y))) ||
+ match(FalseVal, m_SDiv(m_Specific(X), m_Value(Y))) ||
+ match(FalseVal, m_UDiv(m_Specific(X), m_Value(Y))) ||
+ match(FalseVal, m_c_UMin(m_Specific(X), m_Value(Y))))) {
+ return nullptr;
+ }
+
auto *ZeroC = cast<Constant>(cast<Instruction>(CondVal)->getOperand(1));
auto *MergedC = Constant::mergeUndefsWith(TrueValC, ZeroC);
// If X is compared with 0 then TrueVal could be either zero or undef.
@@ -915,28 +928,15 @@ static Instruction *foldSelectZeroOrFixedOp(SelectInst &SI,
if (!match(MergedC, m_Zero()) && !match(MergedC, m_Undef()))
return nullptr;
- if (match(FalseVal, m_c_Mul(m_Specific(X), m_Value(Y))) ||
- match(FalseVal, m_c_And(m_Specific(X), m_Value(Y))) ||
- match(FalseVal, m_Shl(m_Specific(X), m_Value(Y))) ||
- match(FalseVal, m_AShr(m_Specific(X), m_Value(Y))) ||
- match(FalseVal, m_LShr(m_Specific(X), m_Value(Y))) ||
- match(FalseVal, m_FShl(m_Specific(X), m_Specific(X), m_Value(Y))) ||
- match(FalseVal, m_FShr(m_Specific(X), m_Specific(X), m_Value(Y))) ||
- match(FalseVal, m_SDiv(m_Specific(X), m_Value(Y))) ||
- match(FalseVal, m_UDiv(m_Specific(X), m_Value(Y))) ||
- match(FalseVal, m_c_UMin(m_Specific(X), m_Value(Y)))) {
- auto *FalseValI = cast<Instruction>(FalseVal);
- auto *FrY = IC.InsertNewInstBefore(new FreezeInst(Y, Y->getName() + ".fr"),
- FalseValI->getIterator());
- IC.replaceOperand(*FalseValI,
- FalseValI->getOperand(0) == Y
- ? 0
- : (FalseValI->getOperand(1) == Y ? 1 : 2),
- FrY);
- return IC.replaceInstUsesWith(SI, FalseValI);
- }
-
- return nullptr;
+ auto *FalseValI = cast<Instruction>(FalseVal);
+ auto *FrY = IC.InsertNewInstBefore(new FreezeInst(Y, Y->getName() + ".fr"),
+ FalseValI->getIterator());
+ IC.replaceOperand(*FalseValI,
+ FalseValI->getOperand(0) == Y
+ ? 0
+ : (FalseValI->getOperand(1) == Y ? 1 : 2),
+ FrY);
+ return IC.replaceInstUsesWith(SI, FalseValI);
}
/// Transform patterns such as (a > b) ? a - b : 0 into usub.sat(a, b).
>From c51c4eebfb828549569a2369ca043e26915958c5 Mon Sep 17 00:00:00 2001
From: bababuck <buchner.ryan at gmail.com>
Date: Wed, 9 Jul 2025 11:51:28 -0700
Subject: [PATCH 4/7] Use m_c_Intrinsic<Intrinisic::umin> instead of m_c_UMin
m_c_UMin will also match with an icmp/select pattern which isn't
desired here.
---
llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
index 13cfaf54068b4..7fdaa5f9d7e64 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
@@ -916,7 +916,8 @@ static Instruction *foldSelectZeroOrFixedOp(SelectInst &SI,
match(FalseVal, m_FShr(m_Specific(X), m_Specific(X), m_Value(Y))) ||
match(FalseVal, m_SDiv(m_Specific(X), m_Value(Y))) ||
match(FalseVal, m_UDiv(m_Specific(X), m_Value(Y))) ||
- match(FalseVal, m_c_UMin(m_Specific(X), m_Value(Y))))) {
+ match(FalseVal,
+ m_c_Intrinsic<Intrinsic::umin>(m_Specific(X), m_Value(Y))))) {
return nullptr;
}
>From 1114d55e5205935dd450fb15c57dfa226e0dfa0b Mon Sep 17 00:00:00 2001
From: bababuck <buchner.ryan at gmail.com>
Date: Wed, 9 Jul 2025 12:30:02 -0700
Subject: [PATCH 5/7] Don't match with `shl`, `ashr`, and `ashl` because if the
`shfamt` is too large we can create a `poison` value
---
.../InstCombine/InstCombineSelect.cpp | 3 ---
.../InstCombine/select-fixed-zero.ll | 21 +++++++++++--------
llvm/test/Transforms/InstCombine/select.ll | 7 ++++---
3 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
index 7fdaa5f9d7e64..2b4b070cbdc3f 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
@@ -909,9 +909,6 @@ static Instruction *foldSelectZeroOrFixedOp(SelectInst &SI,
if (!(match(FalseVal, m_c_Mul(m_Specific(X), m_Value(Y))) ||
match(FalseVal, m_c_And(m_Specific(X), m_Value(Y))) ||
- match(FalseVal, m_Shl(m_Specific(X), m_Value(Y))) ||
- match(FalseVal, m_AShr(m_Specific(X), m_Value(Y))) ||
- match(FalseVal, m_LShr(m_Specific(X), m_Value(Y))) ||
match(FalseVal, m_FShl(m_Specific(X), m_Specific(X), m_Value(Y))) ||
match(FalseVal, m_FShr(m_Specific(X), m_Specific(X), m_Value(Y))) ||
match(FalseVal, m_SDiv(m_Specific(X), m_Value(Y))) ||
diff --git a/llvm/test/Transforms/InstCombine/select-fixed-zero.ll b/llvm/test/Transforms/InstCombine/select-fixed-zero.ll
index 27a404ad2c8bd..1cf40d087e964 100644
--- a/llvm/test/Transforms/InstCombine/select-fixed-zero.ll
+++ b/llvm/test/Transforms/InstCombine/select-fixed-zero.ll
@@ -30,9 +30,10 @@ define i64 @mul_select(i64 %a, i64 %b) {
; (select (icmp x, 0, eq), 0, (shl x, y)) -> (shl x, y)
define i64 @shl_select(i64 %a, i64 %b) {
; CHECK-LABEL: @shl_select(
-; CHECK-NEXT: [[B_FR:%.*]] = freeze i64 [[B:%.*]]
-; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[A:%.*]], [[B_FR]]
-; CHECK-NEXT: ret i64 [[SHL]]
+; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[A:%.*]], 0
+; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[A]], [[B_FR:%.*]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], i64 0, i64 [[SHL]]
+; CHECK-NEXT: ret i64 [[SELECT]]
;
%cond = icmp eq i64 %a, 0
%shl = shl i64 %a, %b
@@ -56,9 +57,10 @@ define i64 @and_select(i64 %a, i64 %b) {
; (select (icmp x, 0, ne), (ashr x, y), 0) -> (ashr x, y)
define i64 @ashr_select(i64 %a, i64 %b) {
; CHECK-LABEL: @ashr_select(
-; CHECK-NEXT: [[B_FR:%.*]] = freeze i64 [[B:%.*]]
-; CHECK-NEXT: [[ASHR:%.*]] = ashr i64 [[A:%.*]], [[B_FR]]
-; CHECK-NEXT: ret i64 [[ASHR]]
+; CHECK-NEXT: [[COND_NOT:%.*]] = icmp eq i64 [[A:%.*]], 0
+; CHECK-NEXT: [[ASHR:%.*]] = ashr i64 [[A]], [[B_FR:%.*]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND_NOT]], i64 0, i64 [[ASHR]]
+; CHECK-NEXT: ret i64 [[SELECT]]
;
%cond = icmp ne i64 0, %a
%ashr = ashr i64 %a, %b
@@ -69,9 +71,10 @@ define i64 @ashr_select(i64 %a, i64 %b) {
; (select (icmp x, 0, ne), (lshr x, y), 0) -> (lshr x, y)
define i64 @lshr_select(i64 %a, i64 %b) {
; CHECK-LABEL: @lshr_select(
-; CHECK-NEXT: [[B_FR:%.*]] = freeze i64 [[B:%.*]]
-; CHECK-NEXT: [[LSHR:%.*]] = lshr i64 [[A:%.*]], [[B_FR]]
-; CHECK-NEXT: ret i64 [[LSHR]]
+; CHECK-NEXT: [[COND_NOT:%.*]] = icmp eq i64 [[A:%.*]], 0
+; CHECK-NEXT: [[LSHR:%.*]] = lshr i64 [[A]], [[B_FR:%.*]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND_NOT]], i64 0, i64 [[LSHR]]
+; CHECK-NEXT: ret i64 [[SELECT]]
;
%cond = icmp ne i64 0, %a
%lshr = lshr i64 %a, %b
diff --git a/llvm/test/Transforms/InstCombine/select.ll b/llvm/test/Transforms/InstCombine/select.ll
index fa54b38d55171..1f9ee83536016 100644
--- a/llvm/test/Transforms/InstCombine/select.ll
+++ b/llvm/test/Transforms/InstCombine/select.ll
@@ -2733,9 +2733,10 @@ define void @select_freeze_icmp_multuses(i32 %x, i32 %y) {
define i32 @pr47322_more_poisonous_replacement(i32 %arg) {
; CHECK-LABEL: @pr47322_more_poisonous_replacement(
-; CHECK-NEXT: [[TRAILING:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[ARG:%.*]], i1 true)
-; CHECK-NEXT: [[TRAILING_FR:%.*]] = freeze i32 [[TRAILING]]
-; CHECK-NEXT: [[R1_SROA_0_1:%.*]] = lshr exact i32 [[ARG]], [[TRAILING_FR]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[ARG:%.*]], 0
+; CHECK-NEXT: [[TRAILING:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[ARG]], i1 true)
+; CHECK-NEXT: [[SHIFTED:%.*]] = lshr exact i32 [[ARG]], [[TRAILING]]
+; CHECK-NEXT: [[R1_SROA_0_1:%.*]] = select i1 [[CMP]], i32 0, i32 [[SHIFTED]]
; CHECK-NEXT: ret i32 [[R1_SROA_0_1]]
;
%cmp = icmp eq i32 %arg, 0
>From c5587020c1dbd73324c9a3b17e9e3e6bf078848c Mon Sep 17 00:00:00 2001
From: bababuck <buchner.ryan at gmail.com>
Date: Wed, 9 Jul 2025 14:28:00 -0700
Subject: [PATCH 6/7] Don't match with `udiv` and `sdiv` because if the
denominator is 0 we can create `undef` value
---
.../Transforms/InstCombine/InstCombineSelect.cpp | 2 --
.../Transforms/InstCombine/select-fixed-zero.ll | 14 ++++++++------
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
index 2b4b070cbdc3f..72c03d12c4bc8 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
@@ -911,8 +911,6 @@ static Instruction *foldSelectZeroOrFixedOp(SelectInst &SI,
match(FalseVal, m_c_And(m_Specific(X), m_Value(Y))) ||
match(FalseVal, m_FShl(m_Specific(X), m_Specific(X), m_Value(Y))) ||
match(FalseVal, m_FShr(m_Specific(X), m_Specific(X), m_Value(Y))) ||
- match(FalseVal, m_SDiv(m_Specific(X), m_Value(Y))) ||
- match(FalseVal, m_UDiv(m_Specific(X), m_Value(Y))) ||
match(FalseVal,
m_c_Intrinsic<Intrinsic::umin>(m_Specific(X), m_Value(Y))))) {
return nullptr;
diff --git a/llvm/test/Transforms/InstCombine/select-fixed-zero.ll b/llvm/test/Transforms/InstCombine/select-fixed-zero.ll
index 1cf40d087e964..dc7f37d1ad1bb 100644
--- a/llvm/test/Transforms/InstCombine/select-fixed-zero.ll
+++ b/llvm/test/Transforms/InstCombine/select-fixed-zero.ll
@@ -125,9 +125,10 @@ define i64 @fshr_select_no_combine(i64 %a, i64 %b, i64 %c) {
; (select (icmp x, 0, eq), 0, (sdiv x, y)) -> (sdiv x, y)
define i64 @sdiv_select(i64 %a, i64 %b) {
; CHECK-LABEL: @sdiv_select(
-; CHECK-NEXT: [[B_FR:%.*]] = freeze i64 [[B:%.*]]
-; CHECK-NEXT: [[DIV:%.*]] = sdiv i64 [[A:%.*]], [[B_FR]]
-; CHECK-NEXT: ret i64 [[DIV]]
+; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[A:%.*]], 0
+; CHECK-NEXT: [[DIV:%.*]] = sdiv i64 [[A]], [[B_FR:%.*]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], i64 0, i64 [[DIV]]
+; CHECK-NEXT: ret i64 [[SELECT]]
;
%cond = icmp eq i64 %a, 0
%div = sdiv i64 %a, %b
@@ -138,9 +139,10 @@ define i64 @sdiv_select(i64 %a, i64 %b) {
; (select (icmp x, 0, eq), 0, (udiv x, y)) -> (udiv x, y)
define i64 @udiv_select(i64 %a, i64 %b) {
; CHECK-LABEL: @udiv_select(
-; CHECK-NEXT: [[B_FR:%.*]] = freeze i64 [[B:%.*]]
-; CHECK-NEXT: [[DIV:%.*]] = udiv i64 [[A:%.*]], [[B_FR]]
-; CHECK-NEXT: ret i64 [[DIV]]
+; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[A:%.*]], 0
+; CHECK-NEXT: [[DIV:%.*]] = udiv i64 [[A]], [[B_FR:%.*]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], i64 0, i64 [[DIV]]
+; CHECK-NEXT: ret i64 [[SELECT]]
;
%cond = icmp eq i64 %a, 0
%div = udiv i64 %a, %b
>From 3e8c74fdbaabd0a92973ebffb0518631d4da32ed Mon Sep 17 00:00:00 2001
From: bababuck <buchner.ryan at gmail.com>
Date: Thu, 10 Jul 2025 09:31:28 -0700
Subject: [PATCH 7/7] Add back in SDiv/UDiv/URem/SRem, but don't freeze them
---
.../InstCombine/InstCombineSelect.cpp | 36 ++++++++++++-------
.../InstCombine/select-fixed-zero.ll | 24 +++++--------
2 files changed, 31 insertions(+), 29 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
index 72c03d12c4bc8..9d62533d93c0a 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
@@ -907,12 +907,20 @@ static Instruction *foldSelectZeroOrFixedOp(SelectInst &SI,
if (TrueValC == nullptr || !isa<Instruction>(FalseVal))
return nullptr;
- if (!(match(FalseVal, m_c_Mul(m_Specific(X), m_Value(Y))) ||
- match(FalseVal, m_c_And(m_Specific(X), m_Value(Y))) ||
- match(FalseVal, m_FShl(m_Specific(X), m_Specific(X), m_Value(Y))) ||
- match(FalseVal, m_FShr(m_Specific(X), m_Specific(X), m_Value(Y))) ||
- match(FalseVal,
- m_c_Intrinsic<Intrinsic::umin>(m_Specific(X), m_Value(Y))))) {
+ bool FreezeY;
+ if (match(FalseVal, m_c_Mul(m_Specific(X), m_Value(Y))) ||
+ match(FalseVal, m_c_And(m_Specific(X), m_Value(Y))) ||
+ match(FalseVal, m_FShl(m_Specific(X), m_Specific(X), m_Value(Y))) ||
+ match(FalseVal, m_FShr(m_Specific(X), m_Specific(X), m_Value(Y))) ||
+ match(FalseVal,
+ m_c_Intrinsic<Intrinsic::umin>(m_Specific(X), m_Value(Y)))) {
+ FreezeY = true;
+ } else if (match(FalseVal, m_SDiv(m_Specific(X), m_Value(Y))) ||
+ match(FalseVal, m_UDiv(m_Specific(X), m_Value(Y))) ||
+ match(FalseVal, m_SRem(m_Specific(X), m_Value(Y))) ||
+ match(FalseVal, m_URem(m_Specific(X), m_Value(Y)))) {
+ FreezeY = false;
+ } else {
return nullptr;
}
@@ -925,13 +933,15 @@ static Instruction *foldSelectZeroOrFixedOp(SelectInst &SI,
return nullptr;
auto *FalseValI = cast<Instruction>(FalseVal);
- auto *FrY = IC.InsertNewInstBefore(new FreezeInst(Y, Y->getName() + ".fr"),
- FalseValI->getIterator());
- IC.replaceOperand(*FalseValI,
- FalseValI->getOperand(0) == Y
- ? 0
- : (FalseValI->getOperand(1) == Y ? 1 : 2),
- FrY);
+ if (FreezeY) {
+ auto *FrY = IC.InsertNewInstBefore(new FreezeInst(Y, Y->getName() + ".fr"),
+ FalseValI->getIterator());
+ IC.replaceOperand(*FalseValI,
+ FalseValI->getOperand(0) == Y
+ ? 0
+ : (FalseValI->getOperand(1) == Y ? 1 : 2),
+ FrY);
+ }
return IC.replaceInstUsesWith(SI, FalseValI);
}
diff --git a/llvm/test/Transforms/InstCombine/select-fixed-zero.ll b/llvm/test/Transforms/InstCombine/select-fixed-zero.ll
index dc7f37d1ad1bb..6b436f4819057 100644
--- a/llvm/test/Transforms/InstCombine/select-fixed-zero.ll
+++ b/llvm/test/Transforms/InstCombine/select-fixed-zero.ll
@@ -125,10 +125,8 @@ define i64 @fshr_select_no_combine(i64 %a, i64 %b, i64 %c) {
; (select (icmp x, 0, eq), 0, (sdiv x, y)) -> (sdiv x, y)
define i64 @sdiv_select(i64 %a, i64 %b) {
; CHECK-LABEL: @sdiv_select(
-; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[A:%.*]], 0
-; CHECK-NEXT: [[DIV:%.*]] = sdiv i64 [[A]], [[B_FR:%.*]]
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], i64 0, i64 [[DIV]]
-; CHECK-NEXT: ret i64 [[SELECT]]
+; CHECK-NEXT: [[DIV:%.*]] = sdiv i64 [[A:%.*]], [[B_FR:%.*]]
+; CHECK-NEXT: ret i64 [[DIV]]
;
%cond = icmp eq i64 %a, 0
%div = sdiv i64 %a, %b
@@ -139,10 +137,8 @@ define i64 @sdiv_select(i64 %a, i64 %b) {
; (select (icmp x, 0, eq), 0, (udiv x, y)) -> (udiv x, y)
define i64 @udiv_select(i64 %a, i64 %b) {
; CHECK-LABEL: @udiv_select(
-; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[A:%.*]], 0
-; CHECK-NEXT: [[DIV:%.*]] = udiv i64 [[A]], [[B_FR:%.*]]
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], i64 0, i64 [[DIV]]
-; CHECK-NEXT: ret i64 [[SELECT]]
+; CHECK-NEXT: [[DIV:%.*]] = udiv i64 [[A:%.*]], [[B_FR:%.*]]
+; CHECK-NEXT: ret i64 [[DIV]]
;
%cond = icmp eq i64 %a, 0
%div = udiv i64 %a, %b
@@ -153,10 +149,8 @@ define i64 @udiv_select(i64 %a, i64 %b) {
; (select (icmp x, 0, eq), 0, (srem x, y)) -> (srem x, y)
define i64 @srem_select(i64 %a, i64 %b) {
; CHECK-LABEL: @srem_select(
-; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[A:%.*]], 0
-; CHECK-NEXT: [[REM:%.*]] = srem i64 [[A]], [[B:%.*]]
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], i64 0, i64 [[REM]]
-; CHECK-NEXT: ret i64 [[SELECT]]
+; CHECK-NEXT: [[REM:%.*]] = srem i64 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i64 [[REM]]
;
%cond = icmp eq i64 %a, 0
%rem = srem i64 %a, %b
@@ -167,10 +161,8 @@ define i64 @srem_select(i64 %a, i64 %b) {
; (select (icmp x, 0, eq), 0, (urem x, y)) -> (urem x, y)
define i64 @urem_select(i64 %a, i64 %b) {
; CHECK-LABEL: @urem_select(
-; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[A:%.*]], 0
-; CHECK-NEXT: [[REM:%.*]] = urem i64 [[A]], [[B:%.*]]
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], i64 0, i64 [[REM]]
-; CHECK-NEXT: ret i64 [[SELECT]]
+; CHECK-NEXT: [[REM:%.*]] = urem i64 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i64 [[REM]]
;
%cond = icmp eq i64 %a, 0
%rem = urem i64 %a, %b
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