[llvm] [AMDGPU] Add DAG mutation to improve scheduling before barriers (PR #142716)

[Carl Ritson via llvm-commits]

================
@@ -0,0 +1,87 @@
+//===--- AMDGPUBarrierLatency.cpp - AMDGPU Barrier Latency ----------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+/// \file This file contains a DAG scheduling mutation to add latency to
+///       barrier edges between ATOMIC_FENCE instructions and preceeding
+///       memory accesses potentially affected by the fence.
+///       This is beneficial when a fence would cause wait count insertion,
+///       as more instructions will be scheduled before the fence hiding
+///       memory latency.
+///       It also reduces the risk of a fence causing a premature wait
+///       on all active memory operations.
+//
+//===----------------------------------------------------------------------===//
+
+#include "AMDGPUBarrierLatency.h"
+#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
+#include "SIInstrInfo.h"
+#include "llvm/CodeGen/ScheduleDAGInstrs.h"
+
+using namespace llvm;
+
+namespace {
+
+class BarrierLatency : public ScheduleDAGMutation {
+public:
+  BarrierLatency() = default;
+  void apply(ScheduleDAGInstrs *DAG) override;
+};
+
+static bool isMemLoad(const MachineInstr *MI) {
+  auto isLoad = [](const MachineInstr *MI) {
+    return (SIInstrInfo::isDS(*MI) || SIInstrInfo::isVMEM(*MI) ||
+            SIInstrInfo::isSMRD(*MI)) &&
+           MI->mayLoad();
----------------
perlfu wrote:

Thanks! I think when I wrote this originally I was targeting specific types of load.  However it makes sense to simplify this to all loads.

https://github.com/llvm/llvm-project/pull/142716