[llvm] [AMDGPU] Support function attribute to override postRA scheduling direction (PR #147708)
Harrison Hao via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 13 18:51:56 PDT 2025
https://github.com/harrisonGPU updated https://github.com/llvm/llvm-project/pull/147708
>From ea360350ce6320fcb70b2ce440468aba0767bb79 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Wed, 9 Jul 2025 17:46:23 +0800
Subject: [PATCH 1/3] [AMDGPU] Support function attribute to override postRA
scheduling direction
---
llvm/include/llvm/CodeGen/MachineScheduler.h | 1 +
llvm/lib/CodeGen/MachineScheduler.cpp | 2 +-
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 17 +++++++++++++++++
3 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h
index e7a7091acee64..1635eae758590 100644
--- a/llvm/include/llvm/CodeGen/MachineScheduler.h
+++ b/llvm/include/llvm/CodeGen/MachineScheduler.h
@@ -116,6 +116,7 @@ enum Direction {
} // namespace MISched
LLVM_ABI extern cl::opt<MISched::Direction> PreRADirection;
+LLVM_ABI extern cl::opt<MISched::Direction> PostRADirection;
LLVM_ABI extern cl::opt<bool> VerifyScheduling;
#ifndef NDEBUG
extern cl::opt<bool> ViewMISchedDAGs;
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 76cba2949af60..72e1fce07f33e 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -190,7 +190,7 @@ cl::opt<MISched::Direction> PreRADirection(
clEnumValN(MISched::Bidirectional, "bidirectional",
"Force bidirectional pre reg-alloc list scheduling")));
-static cl::opt<MISched::Direction> PostRADirection(
+cl::opt<MISched::Direction> PostRADirection(
"misched-postra-direction", cl::Hidden,
cl::desc("Post reg-alloc list scheduling direction"),
cl::init(MISched::Unspecified),
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index c3536113e9bef..4c46e703b4604 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1144,6 +1144,23 @@ GCNTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
ScheduleDAGInstrs *
GCNTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
+ Attribute PostRADirectionAttr =
+ C->MF->getFunction().getFnAttribute("misched-postra-direction");
+
+ if (PostRADirectionAttr.isValid()) {
+ StringRef PostRADirectionStr = PostRADirectionAttr.getValueAsString();
+ if (PostRADirectionStr == "topdown")
+ PostRADirection = MISched::TopDown;
+ else if (PostRADirectionStr == "bottomup")
+ PostRADirection = MISched::BottomUp;
+ else if (PostRADirectionStr == "bidirectional")
+ PostRADirection = MISched::Bidirectional;
+ else
+ report_fatal_error(
+ Twine("invalid value for 'misched-postra-direction' attribute: ") +
+ PostRADirectionStr);
+ }
+
ScheduleDAGMI *DAG =
new GCNPostScheduleDAGMILive(C, std::make_unique<PostGenericScheduler>(C),
/*RemoveKillFlags=*/true);
>From 220345b8465729cea3b7c47fc92fbf4792034325 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Sun, 13 Jul 2025 20:54:37 +0800
Subject: [PATCH 2/3] [AMDGPU] Add a new attr and lit test.
---
llvm/lib/CodeGen/MachineScheduler.cpp | 19 ++++++++++
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 19 +++++++---
.../CodeGen/AMDGPU/postra-sched-attribute.ll | 38 +++++++++++++++++++
3 files changed, 71 insertions(+), 5 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 72e1fce07f33e..f1d5b90ed0fb2 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -4352,6 +4352,25 @@ void PostGenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
RegionPolicy.OnlyTopDown = false;
}
+ LLVM_DEBUG({
+ const char *DirStr = "default";
+ switch (PostRADirection) {
+ case MISched::TopDown:
+ DirStr = "topdown";
+ break;
+ case MISched::BottomUp:
+ DirStr = "bottomup";
+ break;
+ case MISched::Bidirectional:
+ DirStr = "bidirectional";
+ break;
+ default:;
+ }
+
+ dbgs() << "Post-MI-sched direction (" << MF.getName() << "): " << DirStr
+ << '\n';
+ });
+
BotIdx = NumRegionInstrs - 1;
this->NumRegionInstrs = NumRegionInstrs;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 4c46e703b4604..8ca67775efb9b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -456,6 +456,11 @@ static cl::opt<std::string>
cl::desc("Select custom AMDGPU scheduling strategy."),
cl::Hidden, cl::init(""));
+static cl::opt<std::string>
+ AMDGPUPostRADirection("amdgpu-post-ra-direction",
+ cl::desc("Select custom AMDGPU postRA direction."),
+ cl::Hidden, cl::init(""));
+
static cl::opt<bool> EnableRewritePartialRegUses(
"amdgpu-enable-rewrite-partial-reg-uses",
cl::desc("Enable rewrite partial reg uses pass"), cl::init(true),
@@ -1145,7 +1150,7 @@ GCNTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
ScheduleDAGInstrs *
GCNTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
Attribute PostRADirectionAttr =
- C->MF->getFunction().getFnAttribute("misched-postra-direction");
+ C->MF->getFunction().getFnAttribute("amdgpu-post-ra-direction");
if (PostRADirectionAttr.isValid()) {
StringRef PostRADirectionStr = PostRADirectionAttr.getValueAsString();
@@ -1155,10 +1160,14 @@ GCNTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
PostRADirection = MISched::BottomUp;
else if (PostRADirectionStr == "bidirectional")
PostRADirection = MISched::Bidirectional;
- else
- report_fatal_error(
- Twine("invalid value for 'misched-postra-direction' attribute: ") +
- PostRADirectionStr);
+ else {
+ PostRADirection = MISched::Unspecified;
+ DiagnosticInfoOptimizationFailure Diag(
+ C->MF->getFunction(), C->MF->getFunction().getSubprogram(),
+ Twine("invalid value for postRa direction attribute: '") +
+ PostRADirectionStr);
+ C->MF->getFunction().getContext().diagnose(Diag);
+ }
}
ScheduleDAGMI *DAG =
diff --git a/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll b/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll
new file mode 100644
index 0000000000000..7d9422d81c129
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll
@@ -0,0 +1,38 @@
+; REQUIRES: asserts
+
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -debug-only=machine-scheduler < %s 2>&1 | FileCheck %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s 2>&1 | FileCheck -check-prefixes=WARNING %s
+
+; CHECK-LABEL: {{^}}postra-sched-topdown:
+; CHECK: Post-MI-sched direction (postra-sched-topdown): topdown
+define float @postra-sched-topdown(float %input) nounwind #0 {
+ %x = fadd float %input, 1.000000e+00
+ ret float %x
+}
+
+; CHECK-LABEL: {{^}}postra-sched-bottomup:
+; CHECK: Post-MI-sched direction (postra-sched-bottomup): bottomup
+define float @postra-sched-bottomup(float %input) nounwind #1 {
+ %x = fsub float %input, 1.000000e+00
+ ret float %x
+}
+
+; CHECK-LABEL: {{^}}postra-sched-bidirectional:
+; CHECK: Post-MI-sched direction (postra-sched-bidirectional): bidirectional
+define float @postra-sched-bidirectional(float %input) nounwind #2 {
+ %x = fadd float %input, 1.000000e+00
+ ret float %x
+}
+
+; CHECK-LABEL: {{^}}postra-sched-warning:
+; CHECK: Post-MI-sched direction (postra-sched-warning): default
+; WARNING: invalid value for postRa direction attribute
+define float @postra-sched-warning(float %input) nounwind #3 {
+ %x = fsub float %input, 1.000000e+00
+ ret float %x
+}
+
+attributes #0 = { alwaysinline nounwind memory(readwrite) "amdgpu-post-ra-direction"="topdown"}
+attributes #1 = { alwaysinline nounwind memory(readwrite) "amdgpu-post-ra-direction"="bottomup"}
+attributes #2 = { alwaysinline nounwind memory(readwrite) "amdgpu-post-ra-direction"="bidirectional"}
+attributes #3 = { alwaysinline nounwind memory(readwrite) "amdgpu-post-ra-direction"="warning"}
>From 99be971c68f80d6d42240a61ef94e65d6fdd014a Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Mon, 14 Jul 2025 09:51:36 +0800
Subject: [PATCH 3/3] [AMDGPU] Remove other att.
---
llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll b/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll
index 7d9422d81c129..c6f63f3b4a1b3 100644
--- a/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll
+++ b/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll
@@ -32,7 +32,7 @@ define float @postra-sched-warning(float %input) nounwind #3 {
ret float %x
}
-attributes #0 = { alwaysinline nounwind memory(readwrite) "amdgpu-post-ra-direction"="topdown"}
-attributes #1 = { alwaysinline nounwind memory(readwrite) "amdgpu-post-ra-direction"="bottomup"}
-attributes #2 = { alwaysinline nounwind memory(readwrite) "amdgpu-post-ra-direction"="bidirectional"}
-attributes #3 = { alwaysinline nounwind memory(readwrite) "amdgpu-post-ra-direction"="warning"}
+attributes #0 = {"amdgpu-post-ra-direction"="topdown"}
+attributes #1 = {"amdgpu-post-ra-direction"="bottomup"}
+attributes #2 = {"amdgpu-post-ra-direction"="bidirectional"}
+attributes #3 = {"amdgpu-post-ra-direction"="warning"}
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