[llvm] 2886d30 - [RISCV] Add short forward branch scheduling for Andes45 (#147890)

[via llvm-commits]

Author: Jim Lin
Date: 2025-07-14T09:26:19+08:00
New Revision: 2886d30dd68f798deda7093d00bf9fc52dabcdd7

URL: https://github.com/llvm/llvm-project/commit/2886d30dd68f798deda7093d00bf9fc52dabcdd7
DIFF: https://github.com/llvm/llvm-project/commit/2886d30dd68f798deda7093d00bf9fc52dabcdd7.diff

LOG: [RISCV] Add short forward branch scheduling for Andes45 (#147890)

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVSchedAndes45.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
index da0ceee0c0840..5ef858a787c7c 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
@@ -54,6 +54,12 @@ def : WriteRes<WriteShiftImm32, [Andes45ALU]>;
 def : WriteRes<WriteShiftReg, [Andes45ALU]>;
 def : WriteRes<WriteShiftReg32, [Andes45ALU]>;
 
+// Short forward branch
+def : WriteRes<WriteSFB, [Andes45ALU]> {
+  let Latency = 1;
+  let NumMicroOps = 2;
+}
+
 // Branching
 def : WriteRes<WriteJmp, [Andes45ALU]>;
 def : WriteRes<WriteJal, [Andes45ALU]>;
@@ -231,6 +237,8 @@ def : ReadAdvance<ReadShiftImm, 0>;
 def : ReadAdvance<ReadShiftImm32, 0>;
 def : ReadAdvance<ReadShiftReg, 0>;
 def : ReadAdvance<ReadShiftReg32, 0>;
+def : ReadAdvance<ReadSFBJmp, 0>;
+def : ReadAdvance<ReadSFBALU, 0>;
 def : ReadAdvance<ReadJalr, 0>;
 def : ReadAdvance<ReadJmp, 0>;
 def : ReadAdvance<ReadIMul, 0>;
@@ -328,7 +336,6 @@ def : ReadAdvance<ReadCSR, 0>;
 //===----------------------------------------------------------------------===//
 // Unsupported extensions
 defm : UnsupportedSchedQ;
-defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedV;
 defm : UnsupportedSchedZabha;
 defm : UnsupportedSchedZbkb;